Hi guys,
This was a question that was sort of missed in our last post, which was getting messy. You guys addressed all of our issues except this one, so I thought I would just make a new post:
During the measurement of power up sequence I noticed the amplitude of SYSOSC_IN is kind of small as you can see in the below picture.The Ch1(yellow color) is K2G’s SYSOSC_OUT. It swings between 0 to 1.8V. But Ch3(pink color), K2G’s SYSOSC_IN, only swings 0.45V to 1.3V.
Based on the datasheet, the VIL=0.35*1.8V=0.63V; VIH=0.35*1.8V=1.17V. we only have less than 0.2V margin for both VIL and VIH. Is there any concern about it? Do we need to improve it? If so, how? Could it indeed be the crystal's load capacitance, our guess on the last linked post?
Thanks,
Brian
