All-
From the C6472 data sheet, our understanding is that "Port 0" internal L2 memory is per-core SRAM starting at 0x0080 0000, and "Port 1" internal L2 memory is shared mem starting at 0x0010 0000.
But in the memory map given in the data sheet, the first part of the memory map table, labeled "Internal RAM and ROM", shows shared mem at 0x0020 0000. We use that address for data shared between cores, and it seems to work fine. But, the next part of the table, labeled "Internal RAM (Global Memory Map)", gives shared mem addresses like this:
SL2 RAM (through DSP0) 0x1020 0000
SL2 RAM (through DSP1) 0x1120 0000
:
This brings up a couple of questions...
Question 1 -- when we use 0x0020 0000, is this working because it's a 'reflection' of 0x0010 0000?
Question 2 -- when the data sheet uses the term "global", is this from the perspective of HPI or other external peripherals? If so, then does it mean to "go through DSP0"? What happens if we make an HPI access to 0x1020 0000? Is there something that affects core 0 and and not other cores?
-Jeff
