Redundancy Implementation in DSP Processor

Sir I am using a DSP Processor for the purpose of stabilization in an automobile system that is used in rough terrain.

The orientation management is required to maintain the continuity of the display that is fast enough (approx. 250 micro sec.) so that it avoids any kind of distortion in the signal. It receives analog signals from Gyros. The reading of motor, encoder, running of compensator loops, data acquisition results in loading. A further communication requirement will surely result in a delay. Therefore it is important that load on a DSP is less. Hence I am using FPGA , 2 extra micro controllers for maintaining external and internal interfaces and a CAN micro-controller that are interconnected to each other along with DSP Processor. Please refer to the figure.Fig.tif

Sir,

We are not using TI DSP. I am reffering in general terms. I wish to know the architecture of processor redundancy implementation in general and if any TI parts can be useful for the same.

Thanks

KOMAL