TMS320C6678: problem enumerating pcie peripheral

Hi,

Which Processor SDK RTOS version are you using?

Best Regards,
Yordan

i'va checked code in multiple mcsdk and they were same, i tired mcsdk_2_00_06_18 and mcsdk_2_01_00_03

Hi Malek,

I would suggest you to work with the latest C667x RTOS SDK:

www.ti.com/.../processor-sdk-c667x
software-dl.ti.com/.../index_FDS.html

I would also suggest you to compare PCIe related registers between working case and non-working case, and trace if there are any differences.

See also if the below pointers will be in help:

software-dl.ti.com/.../Foundational_Components.html
processors.wiki.ti.com/.../Processor_SDK_RTOS_BOOT_C66x
processors.wiki.ti.com/.../KeyStone_Bootloader.pdf

Regards,
Pavel

hi
i found what's make difference between my code and TI IBL code. there is a line inside "iblEnterRom" function

DEVICE_REG32_W(DEVICE_SPI_BASE(0) + SPI_REG_SPIDAT0,
FPGA_WRITE_REG_CMD(FPGA_ICS557_SEL_CTRL_REG,1));

which by my understanding results in clock to be feed from ASM slot. and also in "iblPCIeWorkaround" function there is this line :

DEVICE_REG32_W ((PCIE_BASE_ADDR + PCIE_LINK_STAT_CTRL), 0x10110080); /* extended sync, slot_clk_cfg = 1 */

which its 28th bit is logical 1. according to ti data sheet this setting will cause for clock to be feed from slot. now here is my new questions:

1. there is an ambiguity here in settings of LINK_STAT_CTRL register. while its 28th bit is 1 to select clock from ASM slot, its 6th bit is zero which means the system is configured for separated clock not for "common clock", can you explain this?
2. i tried to set system clock to be separated both by setting in LINK_STAT_CTRL register and by altering value of FPGA_ICS557_SEL_CTRL_REG to 0, but evm won't get enumerated. does it means that two system with separated clock can't be trained so they detect each other? in another word, is using shared clock a forced condition for a successful enumeration?

malek alashiri said:

1. there is an ambiguity here in settings of LINK_STAT_CTRL register. while its 28th bit is 1 to select clock from ASM slot, its 6th bit is zero which means the system is configured for separated clock not for "common clock", can you explain this?

Yes, you are right, When PCIe common clock architecture is used, then these 3 bits should be set to 1:

LINK_STAT_CTRL [28] SLOT_CLK_CFG, [7] EXT_SYNC, [6] COMMON_CLK_CFG

See below e2e threads for details:

malek alashiri said:

2. i tried to set system clock to be separated both by setting in LINK_STAT_CTRL register and by altering value of FPGA_ICS557_SEL_CTRL_REG to 0, but evm won't get enumerated. does it means that two system with separated clock can't be trained so they detect each other? in another word, is using shared clock a forced condition for a successful enumeration?

You can also use two separate clocks.

Regards,
Pavel

Hi,

For the TMS320C6678 card PCIE enumeration in a PC host setup, you must have to use the common reference clock, that is PC's PCIE reference clock feeding into C6678. In the TI 6678 EVM, we have a FPGA to select the clock source. As you can see in the TI IBL code, FPGA_ICS557_SEL_CTRL_REG is set to 1 to select the clock from PC. If you set this to 0, then they will use two separate clocks on each side, the enumeration will not work.

Now, back to the LINK_STAT_CTRL register in the common reference clock case, the bit 28 (slot_cfg_clk), bit 7 (ext_sync) and bit 6 (common_clk_cfg) should all be set to 1 by reading the PCIE user guide. The TI IBL code is 5-6 years old and never been changed since then, there may be some reasons why set bit 6 = 0 or it is a simple overlook at that time. In our test, we don't see issues with enumeration with PC, so setting bit 6 to 0 or 1 seems didn't cause the issue. 

From your testing with TI IBL, it also worked even with bit6 = 0. In your own IBL code, let's say you selected PCIE reference clock from host PC but still set bit 6=0, did it work? Then, if you set bit6=1, did it work? 

Regards, Eric

hello
sorry it take too long.
we got same response as TI IBL. i mean it seems that bit 6 has no effect and it's only clock source that will cause the problem.
knowing that, i was wondering is it impossible for two device with separated clock to enumerate each other? or to put it simply, let's say we want to clear FPGA_ICS557_SEL_CTRL_REG to zero, now what we should do so that PC enumerate us?
as you know we checked our IBL by setting FPGA_ICS557_SEL_CTRL_REG to 1 and we got enumerated, but then when we clear FPGA_ICS557_SEL_CTRL_REG to 0, we didn't get enumerated. we also try different kind of arrangement for bit 28 (slot_cfg_clk), bit 7 (ext_sync) and bit 6 (common_clk_cfg). it seems these bit have no effect or if they have it's not sufficient for enumeration with separated clock.
thanks in advance