Watchdog timer reset issue in DM648

Hi

I am trying to configure the TIMER2 of DM648 as watchdog timer.

The issue i have is that when the counter registers equals the value in period registers, DSP is not getting reset. I am not writing the special sequence to the WDKEY anywhere in my code.

Also i checked the WDFLAG of the WDTCR register. It is zero when the TIM registers are counting up and gets set to 1 when they finishes counting up, indictaing that a watchdog timeout has indeed occurred. But DSP continues to run even after this.

Can anybody tell if i am missing something.

Have you observed this behavior with a JTAG emulator connected, or have you also observed this behavior when an emulator is not connected and the device is operating in a stand alone fashion?

The behavior was observed without JTAG emulator connection. The devidce was running in standalone fashion.

I suspect that there is some initialization problem going on, particularly since you mention that your code does not write to WDKEY anywhere, since part of the initialization sequence is to write the key to put the watchdog into an active state. I would compare your code to figure 10 from SPRUEL0, in particular that in addition to putting the timer into watchdog mode that you complete the activation sequence by writing in the key value after enabling the WDEN bit. Note that even if you do not get the watchdog to the active state you can still see WDFLAG being set, as one of the events that happens when you get to the active state is the WDFLAG bit being cleared. If you are already doing this initialization sequence than we may have to investigate this further, off hand I do not know of any ways to prevent the watchdog reset outside of the timer configuration.

I think this is the same issue as was posted in https://community.ti.com/forums/t/1287.aspx

My thought on this was that the initialization sequence may be incorrect, since you are required to write the key in as part of the sequence.

EDIT: Merged the threads into one.

WDKEY is written with the required sequence (0xa5c6 followed with 0x0xda7e) as part of the initialization after enabling the WDEN bit. After the watchdog timer configuration, the value in the TIM12 and TIM34 registers are getting incremented. The registers reach the value set in the PRD registers and then TIM12 and TIM34 registers become zero.

When the TIM registers reach the value of the PRD registers, WDFLAG of the WDTCR register is getting set. Following are my observations:

When the Counter registers (TIM12 and TIM34) are incrementing.
        WDEN = 1
        WDFLAG = 0
 When the value in the counter register matches the value in the period registers
        WDEN = 0
        WDFLAG = 1

 

The DSP continues to run without getting reset.

Thank you for clarifying your initialization sequence, it sounds like you are doing everything correctly. This is something we are going to have to investigate internally a bit, it seems you are not the first to run into issues starting up the watchdog timer capability on the DM648. We will be sure to let you know if we have any further information or suggestions to resolve the issue.

Thanks a lot.

It will be of great help if you could provide a solution to this issue.

We've been working behind the scenes on this issue trying to figure out what's going on.  We're still working out all the details as to how this happened, but the bottom line is that the way the timers were implemented in DM648/DM647 the watchdog functionality will not work.  We'll share more information as it becomes available but I wanted to pass this on to you right away so that you don't waste any more time trying to make it work.  I apologize for the frustration and wasted time with this peripheral.

Brad

Thanks for the information.

Is there any update to this?  I would like to use the watchdog functionality but it seems like this may be a futile effort???

Brad Griffis had mentioned in a post that the DM648 watchdog timer does not reset the device.  This functionality was not implemented.  We have been working on getting the documentation updated to reflect this more directly.

Is there a work around for this.  e.g. the ability to reset the device from software?

There is an updated Timer User Guide on the web (spruel0b.pdf) which removes all references to the watchdog timer.  Unfortunately, I don't know of any other way to reset the device through software.

Brian Thomas said:

Is there a work around for this.  e.g. the ability to reset the device from software?

By my understanding there is no software only workaround, there would have to be something external to the device that asserts the reset line. The closest I could think of would be to have the failing watchdog interrupt drive a signal to an external reset mechanism such as via GPIO.