Other Parts Discussed in Thread: OMAP-L138, OMAPL138
Hello
I'm experiencing an unusal problem on my OMAP-L138 system. I'm using McASP for transmitting PCM voice data in my system. MCASP is supplied with an external clock and frame synchronization signal. There are all 16 serializers being used, 8 for transmit and 8 for receive. Serializers are written to/read from using EDMA3 LLD. Clock is 2048kHz, frames have 32 timeslots, 8-bit each.
I narrowed the problem to setting one bit in McASP configuration: when AXR15 pin is set to transmit data, Linux hangs when a first such transmision occurs. Oddly, the DSP works fine and DMA transfers occur. On the oscilloscoe I see a stable stream of 0xD5 (a-law silence) on AXR15 meaning that OMAP drives the pin in a proper manner.
My transmit/receive pins are grouped into pairs, ARX14 and AXR15 being one such pair. When I alter their functions (e. g. AXR14 transmits and AXR15 receives) Linux does not hang. I did not have the chance of testing if OMAP succesfully reads from AXR15 as the rest of my hardware is dependant on AXR15 to transmit and AXR14 to receive. I cannot make any alterations to the connections made because my custom-built board is multilayered.
Here is the code that hangs the system:
mcasp_set_bits(DAVINCI_MCASP_BASE + DAVINCI_MCASP_SRCTL_REG(0), 1); //transmit
mcasp_set_bits(DAVINCI_MCASP_BASE + DAVINCI_MCASP_SRCTL_REG(3), 1); //transmit
mcasp_set_bits(DAVINCI_MCASP_BASE + DAVINCI_MCASP_SRCTL_REG(5), 1); //transmit
mcasp_set_bits(DAVINCI_MCASP_BASE + DAVINCI_MCASP_SRCTL_REG(7), 1); //transmit
mcasp_set_bits(DAVINCI_MCASP_BASE + DAVINCI_MCASP_SRCTL_REG(9), 1); //transmit
mcasp_set_bits(DAVINCI_MCASP_BASE + DAVINCI_MCASP_SRCTL_REG(11), 1); //transmit
mcasp_set_bits(DAVINCI_MCASP_BASE + DAVINCI_MCASP_SRCTL_REG(13), 1); //transmit
mcasp_set_bits(DAVINCI_MCASP_BASE + DAVINCI_MCASP_SRCTL_REG(15), 1); //transmit
mcasp_set_bits(DAVINCI_MCASP_BASE + DAVINCI_MCASP_SRCTL_REG(1), 2); //receive
mcasp_set_bits(DAVINCI_MCASP_BASE + DAVINCI_MCASP_SRCTL_REG(2), 2); //receive
mcasp_set_bits(DAVINCI_MCASP_BASE + DAVINCI_MCASP_SRCTL_REG(4), 2); //receive
mcasp_set_bits(DAVINCI_MCASP_BASE + DAVINCI_MCASP_SRCTL_REG(6), 2); //receive
mcasp_set_bits(DAVINCI_MCASP_BASE + DAVINCI_MCASP_SRCTL_REG(8), 2); //receive
mcasp_set_bits(DAVINCI_MCASP_BASE + DAVINCI_MCASP_SRCTL_REG(10), 2); //receive
mcasp_set_bits(DAVINCI_MCASP_BASE + DAVINCI_MCASP_SRCTL_REG(12), 2); //receive
mcasp_set_bits(DAVINCI_MCASP_BASE + DAVINCI_MCASP_SRCTL_REG(14), 2); //receive
mcasp_set_reg(DAVINCI_MCASP_BASE + DAVINCI_MCASP_PFUNC_REG, 0x00000000); //all pins as McASP
mcasp_set_reg(DAVINCI_MCASP_BASE + DAVINCI_MCASP_PDIR_REG, AXR(0) | AXR(3) | AXR(5) | AXR(7) | AXR(9) | AXR(11) | AXR(13) | AXR(15)); //set as output
AXR is a simple macro:
#define AXR(n) (1<<n)
When I remove AXR(15) from being set in the PDIR register, yet setting AXR15 as a transmit pin, the system does not hang. This means that DMA configuration cannot be responsible the crash.
I tried many different workarounds and made many tests, but with no luck. PINMUX registers are correctly set (double-checked it with the PINMUX utility available on TI's website). Reducing the number of working PCM channels from 16 to 8 does not help either, it's 100% certaing that when OMAP starts transmitting on AXR15 everything goes bad.
Unlikely as it may sound I even started suspecting a hardware flaw. I tested my code on three boards, with identical results. I'm using an early silicon realease: XOMAPL138ZWT. There is no mention of anything similar to what I'm describing in the errata.
I would be grateful if you could look into my problem.
Kind regards.
Szymon Kukliński