• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 99 subscribers
  • Views 837 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

66AK2H14: Can NOR and NAND flash be attached on EMIF16 with same CS#?

Sung-IL
Mastermind 30810 points
Part Number: 66AK2H14

Dear Champs,

Is it possible to attach NOR and NAND flash memory can be attached on EMIF16 with same CS#?

Actually my customer wants to attached 5 devices on EMIF16 as below and I would like to check if this is possible or not and if there is any performance degradation.

I think there should be no issue to FPGAs and CPLD with each CS#, but I'm very new to attach NOR and NAND flash memory on EMIF16 with same CS#.

e.g. FPGA0/1 and CPLD will use CS1 ~ 3, and NOR memory and NAND memory will use same CS0.

if possible, do you think there will be performance degradation in NAND flash memory and NOR flash memory, FPGAs?

The part name of flash memories are as below.

-. NOR Flash : SG29GL01GS ( Spansion )

-. NAND Flash : MT29F32G08ABACAWP-ITZ:A ( MICRON )

Thanks and Best Regards,

SI.

  • 0
    TI__Guru**** 161600 points

    Hi,

    I'd go with an external switch on the CS0, which selects either NOR or NAND. You cannot use both at the same time having them connected on the same CS0 (also I don't think you can have them connected on the CS0 without some kind of differentiation between the nor & nand chips):

    However, I am not sure how things would look like on a sw level, you will need some sw logic to control the switch. You'll also need to implement drivers for both NOR & NAND chips and switch between them.

    Best Regards,
    Yordan

  • 0 in reply to Yordan Kovachev
    TI__Mastermind 46460 points

    SI,

    It should be possible as long as you add extra decoding to make sure that both devices do not respond on the same address.  In additional to this, you will need to account for the additional delay in the decoding as part of the cycle time configuration.

    This implementation has many loads on the EMIF16.  You will also need to address that in the design to make sure that the drivers can accommodate the accumulated trace and pin capacitance and still meet timing.  IBIS modeling should suffice.

    Tom