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Linux/AM5726: EMIF timing T_RTW calculation

Michael Shklyarman
Genius 12710 points
Part Number: AM5726

Tool/software: Linux

Champs,

Need clarification on the above calculation. according to TRM T_RTW is "Minimum number of DDR clock cycles between Read to Write data phases, minus one". Taking for example DDR3 part used on J6 EVM: Micron MT41K512M16HA-125 IT:A. In its datasheet Figure 69: READ (BL8) to WRITE (BL8) shows read to write transition. According to the figure READ-to-WRITE command delay = RL + tCCD + 2tCK - WL=5+4+2-5=6.  Now, examining u-boot code (($uboot/board/ti/dra7xx/evm.c) I see T_RTW being set to 0xC or 0xD for 532Mhz and 666Mhz speed respectively. My questions are:

1. Is the figure 69 in DDR datasheet describes the transaction that T_RTW configures? 

2. If yes, why are we setting it to double the value the DDR datasheet specifies? Is it a safety margin?

3. if this is a safety margin, what's performance impact?

thanks

Michael 

  • 0
    TI__Guru**** 393215 points
    The DDR experts have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Genius 9655 points
    Michael

    Could you help with the EMIF tool register corresponding to the customer board which might be causing confusion?

    T_RTW is a 3-bit field as described in the TRM EMIF_SDRAM_TIMING_1[31:29]. Therefore, the value computed is not 0xC but 0x6 which aligns with what you computed above. Can you verify this again and let me know the issue here?

    Regards, Siva
  • 0 in reply to sivak
    TI__Genius 12710 points
    Siva,

    The u-boot code is the source of confusion. I am looking at the board/ti/dra7xx/evm.c file because J6 EVM uses the exact same DDR memory the customer board does. This code sets the top 4 bits of the EMIF_SDRAM_TIMING_1 register to 0xC or 0xD depending on the speed of the interface. I am not sure why. Would it be possible to get someone from the SW team to comment here?

    thanks!
    Michael
  • 0 in reply to Michael Shklyarman
    TI__Genius 12710 points

    Relevant code snippets are below in red

     62 static const struct emif_regs emif1_ddr3_532_mhz_1cs = {

     63         .sdram_config_init              = 0x61851ab2,

     64         .sdram_config                   = 0x61851ab2,

     65         .sdram_config2                  = 0x08000000,

     66         .ref_ctrl                       = 0x000040F1,

     67         .ref_ctrl_final                 = 0x00001035,

     68         .sdram_tim1                     = 0xCCCF36B3,

     69         .sdram_tim2                     = 0x308F7FDA,

     70         .sdram_tim3                     = 0x427F88A8,

     71         .read_idle_ctrl                 = 0x00050000,

     72         .zq_config                      = 0x0007190B,

     73         .temp_alert_config              = 0x00000000,

     74         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,

     75         .emif_ddr_phy_ctlr_1            = 0x0E24400B,

     76         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,

     77         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,

     78         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,

     79         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,

     80         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,

     81         .emif_rd_wr_lvl_rmp_win         = 0x00000000,

     82         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,

     83         .emif_rd_wr_lvl_ctl             = 0x00000000,

     84         .emif_rd_wr_exec_thresh         = 0x00000305

     85 };

     86

     87 static const struct emif_regs emif2_ddr3_532_mhz_1cs = {

     88         .sdram_config_init              = 0x61851B32,

     89         .sdram_config                   = 0x61851B32,

     90         .sdram_config2                  = 0x08000000,

     91         .ref_ctrl                       = 0x000040F1,

     92         .ref_ctrl_final                 = 0x00001035,

     93         .sdram_tim1                     = 0xCCCF36B3,

     94         .sdram_tim2                     = 0x308F7FDA,

     95         .sdram_tim3                     = 0x427F88A8,

     96         .read_idle_ctrl                 = 0x00050000,

     97         .zq_config                      = 0x0007190B,

     98         .temp_alert_config              = 0x00000000,

     99         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,

    100         .emif_ddr_phy_ctlr_1            = 0x0E24400B,

    101         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,

    102         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,

    103         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,

    104         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,

    105         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,

    106         .emif_rd_wr_lvl_rmp_win         = 0x00000000,

    107         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,

    108         .emif_rd_wr_lvl_ctl             = 0x00000000,

    109         .emif_rd_wr_exec_thresh         = 0x00000305

    110 };

    111

    112 static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {

    113         .sdram_config_init              = 0x61862B32,

    114         .sdram_config                   = 0x61862B32,

    115         .sdram_config2                  = 0x08000000,

    116         .ref_ctrl                       = 0x0000514C,

    117         .ref_ctrl_final                 = 0x0000144A,

    118         .sdram_tim1                     = 0xD113781C,

    119         .sdram_tim2                     = 0x30717FE3,

    120         .sdram_tim3                     = 0x409F86A8,

    121         .read_idle_ctrl                 = 0x00050000,

    122         .zq_config                      = 0x5007190B,

    123         .temp_alert_config              = 0x00000000,

    124         .emif_ddr_phy_ctlr_1_init       = 0x0024400D,

    125         .emif_ddr_phy_ctlr_1            = 0x0E24400D,

    126         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,

    127         .emif_ddr_ext_phy_ctrl_2        = 0x00A400A4,

    128         .emif_ddr_ext_phy_ctrl_3        = 0x00A900A9,

    129         .emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,

    130         .emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,

    131         .emif_rd_wr_lvl_rmp_win         = 0x00000000,

    132         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,

    133         .emif_rd_wr_lvl_ctl             = 0x00000000,

    134         .emif_rd_wr_exec_thresh         = 0x00000305

    135 };

    136

    137 const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {

    138         .sdram_config_init              = 0x61862BB2,

    139         .sdram_config                   = 0x61862BB2,

    140         .sdram_config2                  = 0x00000000,

    141         .ref_ctrl                       = 0x0000514D,

    142         .ref_ctrl_final                 = 0x0000144A,

    143         .sdram_tim1                     = 0xD1137824,

    144         .sdram_tim2                     = 0x30B37FE3,

    145         .sdram_tim3                     = 0x409F8AD8,

    146         .read_idle_ctrl                 = 0x00050000,

    147         .zq_config                      = 0x5007190B,

    148         .temp_alert_config              = 0x00000000,

    149         .emif_ddr_phy_ctlr_1_init       = 0x0824400E,

    150         .emif_ddr_phy_ctlr_1            = 0x0E24400E,

    151         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,

    152         .emif_ddr_ext_phy_ctrl_2        = 0x006B009F,

    153         .emif_ddr_ext_phy_ctrl_3        = 0x006B00A2,

    154         .emif_ddr_ext_phy_ctrl_4        = 0x006B00A8,

    155         .emif_ddr_ext_phy_ctrl_5        = 0x006B00A8,

    156         .emif_rd_wr_lvl_rmp_win         = 0x00000000,

    157         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,

    158         .emif_rd_wr_lvl_ctl             = 0x00000000,

    159         .emif_rd_wr_exec_thresh         = 0x00000305

    160 };

    161

    162 const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {

    163         .sdram_config_init              = 0x61851ab2,

    164         .sdram_config                   = 0x61851ab2,

    165         .sdram_config2                  = 0x08000000,

    166         .ref_ctrl                       = 0x000040F1,

    167         .ref_ctrl_final                 = 0x00001035,

    168         .sdram_tim1                     = 0xCCCF36B3,

    169         .sdram_tim2                     = 0x30BF7FDA,

    170         .sdram_tim3                     = 0x427F8BA8,

    171         .read_idle_ctrl                 = 0x00050000,

    172         .zq_config                      = 0x0007190B,

    173         .temp_alert_config              = 0x00000000,

    174         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,

    175         .emif_ddr_phy_ctlr_1            = 0x0E24400B,

    176         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,

    177         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,

    178         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,

    179         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,

    180         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,

    181         .emif_rd_wr_lvl_rmp_win         = 0x00000000,

    182         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,

    183         .emif_rd_wr_lvl_ctl             = 0x00000000,

    184         .emif_rd_wr_exec_thresh         = 0x00000305

    185 };

    186

    187 const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {

    188         .sdram_config_init              = 0x61851B32,

    189         .sdram_config                   = 0x61851B32,

    190         .sdram_config2                  = 0x08000000,

    191         .ref_ctrl                       = 0x000040F1,

    192         .ref_ctrl_final                 = 0x00001035,

    193         .sdram_tim1                     = 0xCCCF36B3,

    194         .sdram_tim2                     = 0x308F7FDA,

    195         .sdram_tim3                     = 0x427F88A8,

    196         .read_idle_ctrl                 = 0x00050000,

    197         .zq_config                      = 0x0007190B,

    198         .temp_alert_config              = 0x00000000,

    199         .emif_ddr_phy_ctlr_1_init       = 0x0024400B,

    200         .emif_ddr_phy_ctlr_1            = 0x0E24400B,

    201         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,

    202         .emif_ddr_ext_phy_ctrl_2        = 0x00910091,

    203         .emif_ddr_ext_phy_ctrl_3        = 0x00950095,

    204         .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,

    205         .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,

    206         .emif_rd_wr_lvl_rmp_win         = 0x00000000,

    207         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,

    208         .emif_rd_wr_lvl_ctl             = 0x00000000,

    209         .emif_rd_wr_exec_thresh         = 0x00000305

    210 };

    211

    212 const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra76 = {

    213         .sdram_config_init              = 0x61862B32,

    214         .sdram_config                   = 0x61862B32,

    215         .sdram_config2                  = 0x00000000,

    216         .ref_ctrl                       = 0x0000514C,

    217         .ref_ctrl_final                 = 0x0000144A,

    218         .sdram_tim1                     = 0xD113783C,

    219         .sdram_tim2                     = 0x30B47FE3,

    220         .sdram_tim3                     = 0x409F8AD8,

    221         .read_idle_ctrl                 = 0x00050000,

    222         .zq_config                      = 0x5007190B,

    223         .temp_alert_config              = 0x00000000,

    224         .emif_ddr_phy_ctlr_1_init       = 0x0824400D,

    225         .emif_ddr_phy_ctlr_1            = 0x0E24400D,

    226         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,

    227         .emif_ddr_ext_phy_ctrl_2        = 0x006B009F,

    228         .emif_ddr_ext_phy_ctrl_3        = 0x006B00A2,

    229         .emif_ddr_ext_phy_ctrl_4        = 0x006B00A8,

    230         .emif_ddr_ext_phy_ctrl_5        = 0x006B00A8,

    231         .emif_rd_wr_lvl_rmp_win         = 0x00000000,

    232         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,

    233         .emif_rd_wr_lvl_ctl             = 0x00000000,

    234         .emif_rd_wr_exec_thresh         = 0x00000305

    235 };

    236

    237 const struct emif_regs emif_2_regs_ddr3_666_mhz_1cs_dra76 = {

    238         .sdram_config_init              = 0x61862B32,

    239         .sdram_config                   = 0x61862B32,

    240         .sdram_config2                  = 0x00000000,

    241         .ref_ctrl                       = 0x0000514C,

    242         .ref_ctrl_final                 = 0x0000144A,

    243         .sdram_tim1                     = 0xD113781C,

    244         .sdram_tim2                     = 0x30B47FE3,

    245         .sdram_tim3                     = 0x409F8AD8,

    246         .read_idle_ctrl                 = 0x00050000,

    247         .zq_config                      = 0x5007190B,

    248         .temp_alert_config              = 0x00000000,

    249         .emif_ddr_phy_ctlr_1_init       = 0x0824400D,

    250         .emif_ddr_phy_ctlr_1            = 0x0E24400D,

    251         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,

    252         .emif_ddr_ext_phy_ctrl_2        = 0x006B009F,

    253         .emif_ddr_ext_phy_ctrl_3        = 0x006B00A2,

    254         .emif_ddr_ext_phy_ctrl_4        = 0x006B00A8,

    255         .emif_ddr_ext_phy_ctrl_5        = 0x006B00A8,

    256         .emif_rd_wr_lvl_rmp_win         = 0x00000000,

    257         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,

    258         .emif_rd_wr_lvl_ctl             = 0x00000000,

    259         .emif_rd_wr_exec_thresh         = 0x00000305

    260 };

  • 0 in reply to Michael Shklyarman
    TI__Genius 9655 points
    Michael

    OK - As i pointed out earlier, the issue is not related to t_RTW since this is only a 3-bit field and is being computed correctly. The difference in the SDRAM_TIMING_1 register you see between 533MHz clock rate and 666 MHz clock rate is due to the tRP setting.

    When the timings were derived for the board, it looks like the DDR3-1066 speed bin tables were used for 533MHz operation and DDR3-1333 speed bin tables were used for 666 MHz operation even though the memory part is capable of running at higher speeds. Technically, per JEDEC specification, if a memory part is higher speed grade it should be fully compatible with lower speed grades

    Therefore,
    - when running at 533MHz, the tRP corresponding to DDR3-1066 is 13.125ns (equivalent to 7 tCK). This results in a tRP register setting of 6 since the programmed value is -1 of the desired value.
    - when running at 666MHz, the tRP corresponding to DDR3-1333 is 13.5ns (equivalent to 9 tCK). This results in a tRP register setting of 8 since the programmed value is -1 of the desired value.

    The change in the tRP between 6 and 8 is resulting in the SDRAM_TIMING_1 changing between C and D for the different operating speeds. Let me know if you have any further follow-on questions.

    Regards, Siva
  • 0 in reply to sivak
    TI__Genius 9655 points
    Michael

    Please also see this thread:

    e2e.ti.com/.../707911

    The t_RTW is actually a controller timing parameter. I've provided explanation on the above thread.

    Regards, Siva