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AM5748: DDR ECC feature questions

Michi Yama
Guru 10030 points

Part Number: AM5748

Hi,

I have one question regarding ECC feature of AM5748.

According to the AM574x TRM(spruih8), 15.3.4.14 Error Correction And Detection Feature, it is written the below.

------------------------------------------------------ 

    When the programmed window value is 0x0, that is, window is disabled, and the internal error count meets the programmed threshold, the EMIF will generate
    a 1-bit ECC error interrupt. When servicing the interrupt the error count should be set with a value less than the threshold for triggering the interrupt again.

    When the programmed window value is non-zero, that is, window is enabled, the EMIF will generate a 1-bit ECC error interrupt only if the internal error count
    meets the programmed threshold in that window.

-------------------------------------------------------

I don't know the EMIF's action of the difference by the programmed window value is "0x0" and "non-zero". What is the difference? If the internal error count meets the programmed threshold in window, Is 1-bit ECC error interrupt occurred in spite of  "the window value"? 

Please advise me.

I appreciate your quick reply.

Best regards,

Michi

  • 0
    TI__Mastermind 29385 points
    Michi

    I will have someone answer you question shortly.

    Thanks for your patience

    Paul
  • 0 in reply to PaulM
    TI__Genius 9655 points
    Michi-san

    As described in the TRM, the EMIF_1B_ECC_ERR_THRSH can be used to set a threshold for generating interrupts after the number of 1 bit ECC errors have reached the threshold setting.

    The threshold setting is either window based which is expressed in terms of number of refresh cycles (a non-zero value) in the REG_1B_ECC_ERR_WIN field of the EMIF_1B_ECC_ERR_THRSH register. If the 1-bit ECC errors accumulated in the programmed window exceed the threshold error count, ECC error interrupt is generated.

    Alternately, the window based threshold can be disabled by programming REG_1B_ECC_ERR_WIN to 0. In this case, if the accumulated 1 bit ECC errors exceed the threshold, ECC interrupt is still generated.

    Regards, Siva
  • 0 in reply to sivak
    Guru 10030 points

    Dear　Siva-san,

    Thank you for your explanation.

    I would like to re-confirm you said.

    REG_1B_ECC_ERR_WIN bit field : This bit field should be set same as the REFRESH_RATE bit field  of EMIF_SDRAM_REFRESH_CONTROL[15:0]. Is this correct?

    For exmaple,

    When REG_1B_ECC_ERR_THRSH bit field[31:24]  is set  "0x55"

     REG_1B_ECC_ERR_WIN bit field is 0 : Window is disabled :  An 1-bit ECC error interrupt is generated by EMIF controller when the REG_1B_ECC_ERR_CNT of EMIF_1B_ECC_ERR_CNT register becomes to be 0x55 value. 

     REG_1B_ECC_ERR_WIN bit field is non-zero (it assumes 0xF0F0) : Window is enabled .A 1-bit ECC error is generated by EMIF controller when the REG_1B_ECC_ERR_CNT bit field becomes to be 0x55 value within 0xF0F0.  If REG_1B_ECC_ERR_CNT bit field does not becomes to be 0x55 value within 0xF0F0,  1-bit ECC error interrupt is not generated by EMIF controler, and  the internal error count is reset every window expired(every 0xF0F0 time). But  EMIF_1B_ECC_ERR_CNT register is not cleared.

    Is my understanding right?

    Please advise me again.

    Best regards,

    Michi

  • 0 in reply to Michi Yama
    TI__Genius 9655 points

    Michi-san

    Please see some clarifications below.

    Michi Yama said:

    REG_1B_ECC_ERR_WIN bit field : This bit field should be set same as the REFRESH_RATE bit field  of EMIF_SDRAM_REFRESH_CONTROL[15:0]. Is this correct?

    REG_1B_ECC_ERR_WIN bit field is expressed in terms of number of refresh cycles i.e. if you set this field to a non-zero value. Per your example below if you set to 0xF0F0, the window is 0xF0F0 * REFRESH_RATE cycles (as defined in EMIF_SDRAM_REFRESH_CONTROL[15:0] . 

    Michi Yama said:

    For exmaple,

    When REG_1B_ECC_ERR_THRSH bit field[31:24]  is set  "0x55"

     REG_1B_ECC_ERR_WIN bit field is 0 : Window is disabled :  An 1-bit ECC error interrupt is generated by EMIF controller when the REG_1B_ECC_ERR_CNT of EMIF_1B_ECC_ERR_CNT register becomes to be 0x55 value. 

    Correct. 

    Michi Yama said:

     REG_1B_ECC_ERR_WIN bit field is non-zero (it assumes 0xF0F0) : Window is enabled .A 1-bit ECC error is generated by EMIF controller when the REG_1B_ECC_ERR_CNT bit field becomes to be 0x55 value within 0xF0F0.  If REG_1B_ECC_ERR_CNT bit field does not becomes to be 0x55 value within 0xF0F0,  1-bit ECC error interrupt is not generated by EMIF controler, and  the internal error count is reset every window expired(every 0xF0F0 time). But  EMIF_1B_ECC_ERR_CNT register is not cleared.

    As I mentioned above, the window would be 0xF0F0 refresh cycles if you program the bit field to 0xF0F0 in the REG_1B_ECC_ERR_WIN register bit field. The ECC error interrupt will occur if the error count exceeds the value programmed in REG_1B_ECC_ERR_CNT. IF the error count is less in the window, there is no interrupt generated. The REG_1B_ECC_ERR_CNT will be reset after the window expires

    Hope this is clear now. If this does not explain, let me know the exact issue you have.

    Regards, Siva

  • 0 in reply to sivak
    Guru 10030 points

    Dear Siva-san,

    Thank you for your quick reply.

    I am still confused.

    I know REG_1B_ECC_ERR_THRSH bit field is the threshold for generating 1-bit ECC error interrupt. But I don't know why REG_1B_ECC_ERR_WIN bit field is prepared?

    I think REG_1B_ECC_ERR_WIN bit field is "window", not "threshold" for the interrupt. I think "window" means ”period". If 1bit error count is greater than or equal to the "threshold" within "window" period, the interrupt is generated. Is this right?

    Also you said, "The REG_1B_ECC_ERR_CNT will be reset after the window expires". I don't know the meaning of "window expires". How do I judge "window expires"?  "window" size is defined by REG_1B_ECC_ERR_WIN bit field. But this bit field is not incremented/decremented.

    Please advise me again.

    I appreciate your continuous support.

    Best regards,

    Michi

  • 0 in reply to Michi Yama
    TI__Genius 9655 points

    Michi Yama said:

    I know REG_1B_ECC_ERR_THRSH bit field is the threshold for generating 1-bit ECC error interrupt. But I don't know why REG_1B_ECC_ERR_WIN bit field is prepared?

    I think REG_1B_ECC_ERR_WIN bit field is "window", not "threshold" for the interrupt. I think "window" means ”period". If 1bit error count is greater than or equal to the "threshold" within "window" period, the interrupt is generated. Is this right?

    Your understanding is correct

    Michi Yama said:

    Also you said, "The REG_1B_ECC_ERR_CNT will be reset after the window expires". I don't know the meaning of "window expires". How do I judge "window expires"?  "window" size is defined by REG_1B_ECC_ERR_WIN bit field. But this bit field is not incremented/decremented.

    The window is defined as number of refresh cycles as pointed out earlier. Therefore, the REG_1B_ECC_ERR_WIN register itself is not decremented. The DDR controller counts the number of refresh cycles as defined in  REG_1B_ECC_ERR_WIN bit field to verify the number of ECC 1-bit errors accumulated against the REG_1B_ECC_ERR_THRSH and issues an interrupt if the errors exceed during that duration.

    Regards, Siva