Hello
My customer is currently starting a design with the higher temp spec AM5K2E0x .
As the recomended clocking device only operates to +85degC, they are looking to design a clocking circuit to operate upto +100 (as per the ABDAx variants).
We have looked at the available data sheet, users guides, apps notes, etc.. but are still short of some information, so could you help answer the following :-
The clock input buffers for CORECLK, DDRCLK, NETCPCLK, and SGMIICLK use CVDD as a supply
voltage. These clock inputs are not failsafe and must be held in a high-impedance state until CVDD is at a
valid voltage level. Driving these clock inputs high before CVDD is valid could cause damage to the
device. Once CVDD is valid, it is acceptable that the P and N legs of these clocks may be held in a static
state (either high and low or low and high) until a valid clock frequency is needed at that input.
- Assuming that the above inputs are AC coupled, is it acceptable to de-power the clock circuitry or to set the clock outputs close to 0V as an alternative, or can this damage the device?
- Are the any similar restrictions for the other clock inputs of the device . PCIExCLK, USBCLK, TSREFCLK etc?
Many Thanks
Bob Bacon
