Part Number: AM3703
Hi,
I fully realize that the AM3703 SDRC is designed such that it meets all timing for JEDEC LPDDR1 JC42.3.
However for a particular test a customer needs to run Mentor Hyperlynx DDR simulation and particular timing specs are required to conduct the simulation.
The specific parameters needed are:
tCKAC(min) =
tCKAC(max) =
tCKCTL(min) =
tCKCTL(max) =
tCKDQS(min) =
tCKDQS(max) =
tDQSDQ(min) =
tDQSDQ(max) =
tDS =
tDH =
How can we get access to these timings?
I can provide more detail if needed.
Thanks!
--Gunter
