What is "latched by VD" ?

Dear Manju,

"Any register latched by VD essentially means that the value is "effectively read and retained " by the hardware at every VSYNC."

This reminds me of DRAM (dynamic random access memory), whose contents must be refreshed every few milliseconds. But DRAM is relatively the inferior type of storage device, using the least number of transistors (comparing with SRAM and Flip-Flop) and is the slowest (also compare with SRAM and Flip-Flop). I tend not to believe registers in VPFE are made of DRAM, but most likely should be by Flip-Flops.

So here is what I think:

Regarding what you say, despite the similarity in behavioral pattern (refreshing & read and retained), the purpose is totally different:

1.    For these "latched by VD" registers, at every rising (or perhaps falling, like DDR2?) edge of VSYNC:

1)    If there is a new value, the new value is updated.

2)    If not, the old value is retained.

2.    For DRAM, the frequent refreshing is physically necessary to retain the bit value.

1. Yes , VD refers to VSYNC. Th latching is frequent but that is the expectation otherwise we would not have be having a good experience watching movies if it were slower ( 24 for cinema theaters, 60 for NTSC broadcast and 50 for PAL) . For mobile devices and some others where the display mainly is static most of the times, there are other methods of refresh at a much lower rate to conserve bandwidth.

I don’t really understand this. This “latched by VD” is not related to the refreshing of screen (DDR2 video memory) contents, but is for updating the register value here. Could you expand more on this point?

Sincerely,

Zheng

Dear Manjunath, and welcome others:

I would like to ask a further question:

There are two VSYNCs for each field,

"Any new value of address hat is written into the register will only take effect (effectively read and its contents DMAed) only at the start of the next VSYNC."

I have an understanding which has not been verified by any experiment. Say, someone writes a code which is triggered by interrupt associated with the end of one frame, and that code will change SDR_ADDR so VPFE (or more precisely, DMA. Is this correct?) will write to a new address. When will this new address take effect?

It shall then depend on the time needed until this code line’s (changing SDR_ADDR) completion. If one places the "SDR_ADDR changing" instruction at the beginning of the interrupt service routine code, then in a snap of time the new value is presented to the bus but only latched to SDR_ADDR at the beginning (rising or falling edge?) of the next VSYNC. Since between the end of one frame (at which time the interrupt is triggered) and the start of the next VSYNC there is an interval of time corresponding to more than ten horizontal lines of signal (for NTSC, each file either 312 or 313 lines, but only 288 active. So there are lines during the vertical blanking signal), it may therefore be possible that the forgoing process (execution of the code line for SDR_ADDR change) be completed during this short period, and new SDR_ADDR being effectively latched at the next SYNC. In this manner, the next field will be written by VPFE/DMA to the new updated address designated by the updated SDR_ADDR value.

The above is the assumed "lightning" version of SDR_ADDR change. On the other extreme, if the code line for changing SDR_ADDR is not at the beginning of the said interrupt service routine, but rather at its end or intermediate, and a fairly long computation time has to lapse before the CPU runs to this line (changing SDR_ADDR)'s execution, then it may well be possible for the effective "latched by VD" to happen after a much longer time.

Be Quantitatively:

Define T to be the time taken from the beginning of the interrupt service routine to the end of the execution of this "SDR_ADDR changing" code line.

1. If 30 lines time (assumed. simply because 30 lines time is longer than the interval between one ending VSYNC and the next starting VSYNC) < T < 1/2 field time (assumed, simply because 1/2 field time is shorter than one field time),

then the new SDR_ADDR will definitely be latched at the ending (2nd) VSYNC of the next field

2. If T is much longer, say, T=2.5 fields' time, then counting the next staring VSYNC as the 1st, the new SDR_ADDR will be latched at the 6th VSYNC.

These are my unverified pure reasoning. Are they correct?

The "latched by VD" timing appears to me a very important question. I wish to hear more opinions on this.

Sincerely,

Zheng

Dear Paul,

I think the answer in principle is correct. I will test them with experiments.

Thanks very much, and also to Manju.

Zheng