AM3354: DDR3 configuration delay in U-boot

This is a very old SDK, which has been obsoleted by TI and is no longer maintained or supported. Anyway, the reason for this delay is as follows:
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Initialize SDRAM_REF_CTRL with reset delay value before writing to SDRAM_CONFIG (DDR3 only):

The value in SDRAM _REF_CTRL controls the delay time between the initial rising edge of DDR_RESETn to rising edge of DDR_CKE (JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL should be written with a value of 0x3100 before writing to SDRAM_CONFIG (which initiates a DDR initialization. During first DDR initialization, the sequence should be:

Configure all other EMIF registers
Write SDRAM_REF_CTRL = 0x3100
Write SDRAM_CONFIG with appropriate value
Write SDRAM_REF_CTRL with refresh rate value for normal operation

The value of 0x3100 is derived from the following formula:
(16*SDRAM_REF_CTRL)/400MHz > 500us

Note this value can change based on DDR frequency supported and is only needed for DDR3.
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NOTE: This forum no longer supports SDK 7.0. You should consider moving to the new Processor SDK: www.ti.com/.../PROCESSOR-SDK-AM335X

This is the formula used for calculating the register value needed for the delay. There is no additional information.