As per the data sheet reference below (VDDA_DAC, VDDA1P8V_USBPHY) are grouped in sequence 4 and I understand (VDDS_DPLL_PER_CORE, VDDS_DPLL_MPU_USBHOST) and 1.8 V complex (VDDA_DAC, VDDA1P8V_USBPHY) can be a single 1.8V coming up together for all 4 supplies.
However, in the Logic PD eval board 1.8 V complex (VDDA_DAC, VDDA1P8V_USBPHY) comes up with 3.3 V complex IO (VDDA_3P3V_USBPHY) in sequence 5. Could you suggest which method to follow.
3.5.1 Power-up Sequence
The following steps give an example of power-up sequence supported by the AM3517/05 . 1. IO 1.8V supply (VDDS), Band-gap and LDO supplies (VDDS_SRAM_CORE_BG, VDDS_SRAM_MPU) and oscillator supply (VDDSOSC) should come up first to a stable state. 2. IO 3.3V (VDDSHV) supply should be ramped up next to a stable state. 3. Core (VDD_CORE) supply follows next to a stable state. 4. All the PLL supplies (VDDS_DPLL_PER_CORE, VDDS_DPLL_MPU_USBHOST) and 1.8 V complex IO supplies (VDDA_DAC, VDDA1P8V_USBPHY) should be ramped up next to a stable state. 5. Finally, 3.3 V complex IO (VDDA_3P3V_USBPHY) should be ramped up. 6. sys_nrespwron must be held low at the time the power supplies are ramped up till the time the sys_32k and sys_xtalin clocks are stable.
Thanks, Karthi
