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AM5718: PCIe layout question

Part Number: AM5718

Hello. In "High-Speed Interface Layout Guidelines" in table 4 there is a requirement:

Number of vias allowed on any PCIe/SATA differential trace (Total) 0 Vias

This requirement is quite hard to implement.

In my project with AM5718 on the figure below there are two transitions with vias in TX pair (RX pair without vias) in black rectangle. 

So the question is: does requirement in "High-Speed Interface Layout Guidelines" is reachable anyway in projects and how much critical my mentioned implementation on the figure below?

And additional question. In the same document there is another requirement:

Number of stubs allowed on any differential pair trace (Total) 0 Stubs

As mentioned on figures 16, 17 of this document if via stub is less than 15mils, we dont need to do back-drilling. Is it right and small stub could exist or its critical and back-drilling is required anyway regardless length of stub?