AM3352: DP83867IR configuration

Walter Bonetti

Part Number: AM3352
Other Parts Discussed in Thread: DP83867IR

Hello Team,

I'm working on a custom board based on the BeagleBone Black Rev C design.

I try to use a dp83867ir PHY component in U-Boot. But I can't be able to handle it. It looks very strange comportment. I think it's only able to receive. When I try to setenv an ipaddr and use the ping implementation into U-Boot, It doesn't work.

I started with the U-boot from BeagleBone Black source-code. I have changed some things about the U-Boot config and the board.c, but I can't solve my issue.

Board.c

static struct cpsw_slave_data cpsw_slaves[] = {
	{
		.slave_reg_ofs	= 0x208,
		.sliver_reg_ofs	= 0xd80,
		.phy_addr	= 3, /* set the phyaddr = 0x03 */
		.phy_if		= PHY_INTERFACE_MODE_RGMII, /* use RGMII mode */
	}
};

I have forced the RGMII MODE.

puts("eth0: RGMII MODE\n");
writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);

am335x_boneblack_defconfig

CONFIG_PHYLIB=y
CONFIG_DISABLE_CPSW=y
CONFIG_PHY_TI=y

MII DUMP

=> mdio list
cpsw:
3 - TI DP83867 <--> cpsw
=> mii dump 3 0-5   
0.     (1140)                 -- PHY control register --
  (8000:0000) 0.15    =     0    reset
  (4000:0000) 0.14    =     0    loopback
  (2040:0040) 0. 6,13 =   b10    speed selection = 1000 Mbps
  (1000:1000) 0.12    =     1    A/N enable
  (0800:0000) 0.11    =     0    power-down
  (0400:0000) 0.10    =     0    isolate
  (0200:0000) 0. 9    =     0    restart A/N
  (0100:0100) 0. 8    =     1    duplex = full
  (0080:0000) 0. 7    =     0    collision test enable
  (003f:0000) 0. 5- 0 =     0    (reserved)

1.     (796d)                 -- PHY status register --
  (8000:0000) 1.15    =     0    100BASE-T4 able
  (4000:4000) 1.14    =     1    100BASE-X  full duplex able
  (2000:2000) 1.13    =     1    100BASE-X  half duplex able
  (1000:1000) 1.12    =     1    10 Mbps    full duplex able
  (0800:0800) 1.11    =     1    10 Mbps    half duplex able
  (0400:0000) 1.10    =     0    100BASE-T2 full duplex able
  (0200:0000) 1. 9    =     0    100BASE-T2 half duplex able
  (0100:0100) 1. 8    =     1    extended status
  (0080:0000) 1. 7    =     0    (reserved)
  (0040:0040) 1. 6    =     1    MF preamble suppression
  (0020:0020) 1. 5    =     1    A/N complete
  (0010:0000) 1. 4    =     0    remote fault
  (0008:0008) 1. 3    =     1    A/N able
  (0004:0004) 1. 2    =     1    link status
  (0002:0000) 1. 1    =     0    jabber detect
  (0001:0001) 1. 0    =     1    extended capabilities

2.     (2000)                 -- PHY ID 1 register --
  (ffff:2000) 2.15- 0 =  8192    OUI portion

3.     (a231)                 -- PHY ID 2 register --
  (fc00:a000) 3.15-10 =    40    OUI portion
  (03f0:0230) 3. 9- 4 =    35    manufacturer part number
  (000f:0001) 3. 3- 0 =     1    manufacturer rev. number

4.     (01e1)                 -- Autonegotiation advertisement register --
  (8000:0000) 4.15    =     0    next page able
  (4000:0000) 4.14    =     0    (reserved)
  (2000:0000) 4.13    =     0    remote fault
  (1000:0000) 4.12    =     0    (reserved)
  (0800:0000) 4.11    =     0    asymmetric pause
  (0400:0000) 4.10    =     0    pause enable
  (0200:0000) 4. 9    =     0    100BASE-T4 able
  (0100:0100) 4. 8    =     1    100BASE-TX full duplex able
  (0080:0080) 4. 7    =     1    100BASE-TX able
  (0040:0040) 4. 6    =     1    10BASE-T   full duplex able
  (0020:0020) 4. 5    =     1    10BASE-T   able
  (001f:0001) 4. 4- 0 =     1    selector = IEEE 802.3

5.     (c1e1)                 -- Autonegotiation partner abilities register --
  (8000:8000) 5.15    =     1    next page able
  (4000:4000) 5.14    =     1    acknowledge
  (2000:0000) 5.13    =     0    remote fault
  (1000:0000) 5.12    =     0    (reserved)
  (0800:0000) 5.11    =     0    asymmetric pause able
  (0400:0000) 5.10    =     0    pause able
  (0200:0000) 5. 9    =     0    100BASE-T4 able
  (0100:0100) 5. 8    =     1    100BASE-X full duplex able
  (0080:0080) 5. 7    =     1    100BASE-TX able
  (0040:0040) 5. 6    =     1    10BASE-T full duplex able
  (0020:0020) 5. 5    =     1    10BASE-T able
  (001f:0001) 5. 4- 0 =     1    selector = IEEE 802.3

REGISTER DUMP

=> mii read 3 0-1f
addr=03 reg=00 data=1140
addr=03 reg=01 data=796D
addr=03 reg=02 data=2000
addr=03 reg=03 data=A231
addr=03 reg=04 data=01E1
addr=03 reg=05 data=C1E1
addr=03 reg=06 data=006F
addr=03 reg=07 data=2001
addr=03 reg=08 data=6801
addr=03 reg=09 data=0300
addr=03 reg=0a data=3800
addr=03 reg=0b data=0000
addr=03 reg=0c data=0000
addr=03 reg=0d data=401F
addr=03 reg=0e data=00A8
addr=03 reg=0f data=3000
addr=03 reg=10 data=4040
addr=03 reg=11 data=BC02
addr=03 reg=12 data=0000
addr=03 reg=13 data=1C42
addr=03 reg=14 data=29C7
addr=03 reg=15 data=0000
addr=03 reg=16 data=0000
addr=03 reg=17 data=0040
addr=03 reg=18 data=6150
addr=03 reg=19 data=4444
addr=03 reg=1a data=0002
addr=03 reg=1b data=0000
addr=03 reg=1c data=0000
addr=03 reg=1d data=0000
addr=03 reg=1e data=0002
addr=03 reg=1f data=0000

MY TEST

=> setenv ipaddr 172.16.5.234
=> setenv netmask 255.255.255.0
=> setenv gatewayip 172.16.5.254
=> ping 172.16.5.254
link up on port 0, speed 1000, full duplex
Using cpsw device

I have only a little experiment with Ti-Driver in U-Boot. Maybe, I have missed something or have made a mistake.

If you want to know more information about schematic or source code, ask me. I will be glad to send you more about my issue.

Thank you in advance!

over 7 years ago

0 Pavel Botev over 7 years ago

TI__Guru**** 170625 points

Hi Walter,

Do you use the u-boot that comes with AM335x TI PSDK v4.03?

ti-processor-sdk-linux-am335x-evm-04.03.00.05/board-support/u-boot-2017.01/

CPSW/MDIO mode, pinmux and PHY addr is setup in am335x-bone-common.dtsi

Regards,
Pavel

0 Walter Bonetti over 7 years ago in reply to Pavel Botev

Prodigy 70 points

Hi Pavel,

I use U-Boot version: v2018.01.

cpsw_default: cpsw_default {
		pinctrl-single,pins = <
			/* Slave 1 */
			0x054 (PIN_INPUT_PULLUP | MUX_MODE0)	/* dp83867ir, RESET_N, gpio1_21 */
			0x110 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxerr.mii1_rxerr */
			0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txen.mii1_txen */
			0x118 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxdv.mii1_rxdv */
			0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txd3.mii1_txd3 */
			0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txd2.mii1_txd2 */
			0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txd1.mii1_txd1 */
			0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* mii1_txd0.mii1_txd0 */
			0x12c (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_txclk.mii1_txclk */
			0x130 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxclk.mii1_rxclk */
			0x134 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxd3.mii1_rxd3 */
			0x138 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxd2.mii1_rxd2 */
			0x13c (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxd1.mii1_rxd1 */
			0x140 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mii1_rxd0.mii1_rxd0 */
		>;
	};

	cpsw_sleep: cpsw_sleep {
		pinctrl-single,pins = <
			/* Slave 1 reset value */
			0x054 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* dp83867ir, RESET_N, gpio1_21 */
			0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
		>;
	};

&cpsw_emac0 {
	phy_id = <&davinci_mdio>, <3>;
	phy-mode = "rgmii";
};

&cpsw_emac1 {
	phy_id = <&davinci_mdio>, <1>;
	phy-mode = "mii";
};

&mac {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&cpsw_default>;
	pinctrl-1 = <&cpsw_sleep>;
	status = "okay";
};

&davinci_mdio {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&davinci_mdio_default>;
	pinctrl-1 = <&davinci_mdio_sleep>;
	status = "okay";
};

I read something about the EMAC and the ROM init pins mux of RGMII.

spruh73p : Table 26-31. Pins Used for EMAC Boot in RGMII Mode.

So, I do not know where to begin.

Regards,

0 Pavel Botev over 7 years ago in reply to Walter Bonetti

TI__Guru**** 170625 points

Walter,

Latest AM335x TI PSDK (link below) comes with u-boot v2017.01. Only this u-boot is tested and verified on AM335x boards (EVM, SK, BBB, ICE) and I will recommend you to use that u-boot version.

software-dl.ti.com/.../index_FDS.html

ROM code should be considered only when booting from Ethernet. Do you boot from Ethernet/EMAC/CPSW?

You should start with comparing BBB PHY (LAN8710A) and you custom board PHY (dp83867ir). Check for differences in pinmux, modes, address, speed, and apply these differences in DTS file(s).

Regards,
Pavel

0 Biser Gatchev-XID over 6 years ago

TI__Guru**** 393215 points

Closing this thread due to inactivity. Since there has been no reply from customer for the last 4 months, we consider that this issue has been resolved. If it is not, please start a new thread using the "Ask related question" button.

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AM3352: DP83867IR configuration