Tool/software: TI-RTOS
Hello,
According to the TRM, there two sets of cache maintenance for the IPU M4:
one is under :
7.4.2.1 IPUx_UNICACHE_CFG Register Summary -
CACHE_MAINT 0x55080010 0x58880010
CACHE_MTSTART 0x55080014 0x58880014
CACHE_MTEND 0x55080018 0x58880018
and the second under:
Table 7-48. IPU1_UNICACHE_MMU (AMMU) Registers Mapping Summary -
CACHE_MMU_MAINT 0x55080CA8 0x58880CA8
CACHE_MMU_MTSTART 0x55080CAC 0x58880CAC
CACHE_MMU_MTEND 0x55080CB0 0x58880CB0
CACHE_MMU_MAINTST 0x55080CB4 0x58880CB4
1. Can you please explain what is the difference between these two sets - what is the effect of each of them and when should each be used?
2. From looking at the PDK, it seems the unicache functions act on the first register set only - why?
3. What addresses the MSTART,MEND registers (for each of these sets) should be written to -- physical addresses or virtual addresses (or it does not matter)?
4. For the first set there is no status register and looking at the PDK code it seems that, for example, the invalidate bit is expected to get cleared when invalidation is completed but I could not see the description/explanation on the TRM - can you please describe the full operation of this (and it this also true for the second set or for the second set only the status register should be examined)?
Thanks
Guy
