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IDMA & EDMA conflict?

MattLipsey
Genius 3575 points

I am still experimenting with improving data throughput, and would like to know if I can have a read and a write operating at the same time on a single memory area (not same address).  This would be edma3 bringing data in from DDR2 to L2SRAM while idma1 pages the previous transfer from L2SRAM to L1D, basically using the larger L2 as a middleman for L1 ping pong buffering.  Do these accesses effectively interleave, or does this approach stall one or the other access?  Does Advisory 1.3.11 DSP SDMA/IDMA: Unexpected Stalling and Potential Deadlock Condition When L2 apply to this scheme if I have no L1D cache?

 

DDR2 --- (EDMA3) ---> L2SRAM --- (IDMA1) ---> L1DSRAM ---[ Processing ] --- (EDMA3) ---> DDR2

 

  • TI__Mastermind 41665 points

    MattLipsey said:
    Do these accesses effectively interleave, or does this approach stall one or the other access?

    This gets into the banking structure of the internal memories, in the case of L1D you can have both CPU and DMA/IDMA accessing simultaneously if they access seperate banks of L1D, see section 3.5.1 of SPRU871 for details. In the case of L2 it is not possible to have simultaneous accessors, so the accesses are arbitrated based on the rules in chapter 6 of SPRU871, you will not see interleaving of accesses in L2

    MattLipsey said:
    Does Advisory 1.3.11 DSP SDMA/IDMA: Unexpected Stalling and Potential Deadlock Condition When L2 apply to this scheme if I have no L1D cache?

    Yes, accesses to/from L1D end up with similar effects to when cache writebacks and misses occour with L1D as cache. In general you probably want to at least have some portion of L1D as cache anyway, or every access to data that is not already in L1D will be much slower.