I am still experimenting with improving data throughput, and would like to know if I can have a read and a write operating at the same time on a single memory area (not same address). This would be edma3 bringing data in from DDR2 to L2SRAM while idma1 pages the previous transfer from L2SRAM to L1D, basically using the larger L2 as a middleman for L1 ping pong buffering. Do these accesses effectively interleave, or does this approach stall one or the other access? Does Advisory 1.3.11 DSP SDMA/IDMA: Unexpected Stalling and Potential Deadlock Condition When L2 apply to this scheme if I have no L1D cache?
DDR2 --- (EDMA3) ---> L2SRAM --- (IDMA1) ---> L1DSRAM ---[ Processing ] --- (EDMA3) ---> DDR2