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Linux/DRA75: U-boot cannnot work using only EMIF1 without EMIF2

Part Number: DRA75

Tool/software: Linux

Hi,Sir

We has configured the register and load the code to the SDK PROCESSOR_SDK_VISION_03_03_00_00, the u-boot has no any log output. Then we used u-boot debug and preloaded console, the console log as follows. As we can see, the EMIF2 has initialized. How can we remove the EMIF2 on the SDK?

 >>>>> JYT: sdram_init start------ 
>>sdram_init()
in_sdram = 0
>>>>>JYT: DRA762/752 dmm- else----- 
>>do_sdram_init() 4c000000
>>>>>JYT: DRA752 else case1------ 
>>>>>JYT: DRA752 emif1 752------ 
HW leveling success
<<do_sdram_init() 4c000000
>>do_sdram_init() 4d000000
>>>>>JYT: DRA752 else case1------ 
>>>>>JYT: DRA752 emif1 752------ 
Leveling timeout on EMIF2
<<do_sdram_init() 4d000000
SDRAM: identified size not same as expected size identified: 80 expected: 40000000
<<sdram_init()
 >>>>> JYT: sdram_init completed!------ 
U-Boot SPL 2016.05-00009-gac1d50feef-dirty (Jul 20 2018 - 09:37:55)
 >>>>> JYT: uart it work? ----- 
>>>>>JYT: DRA752 REVISION ------ 
Enable clock domain - 4a009700
Enable clock domain - 4a009300
Enable clock domain - 4a008b00
Enable clock domain - 4a008d00
Enable clock domain - 4a0093c0
Enable clock module - 4a008728
Enable clock module - 4a008b30
Enable clock module - 4a008b38
Enable clock module - 4a008d20
Enable clock module - 4ae07838
Enable clock module - 4a009760
Enable clock module - 4a009768
Enable clock module - 4a009770
Enable clock module - 4a009778
Enable clock module - 4a009780
Enable clock module - 4a009810
Enable clock module - 4a009818
Enable clock module - 4a0093e8
Enable clock module - 4ae07840
Enable clock module - 4a009328
Enable clock module - 4a009330
Enable clock module - 4a009738
Enable clock module - 4ae07830
Enable clock module - 4a009850
Enable clock module - 4a0097a0
Enable clock module - 4a0093d0
Enable clock module - 4a009838
Enable clock module - 4a009388
Enable clock domain - 4a009700
Enable clock domain - 4a009300
Enable clock domain - 4a008b00
Enable clock domain - 4a008d00
Enable clock domain - 4a0093c0
ti_i2c_eeprom_init failed 1
1150 -> optimize_vcore_voltage:efuse 0x4a003b20 bits=16 Vnom=1150, using efuse value 1089
1089
1150 -> optimize_vcore_voltage:efuse 0x4a0025f4 bits=16 Vnom=1150, using efuse value 1054
1054
0 -> 0
1250 -> optimize_vcore_voltage:efuse 0x4a003b10 bits=16 Vnom=1250, using efuse value 1075
1075
1250 -> optimize_vcore_voltage:efuse 0x4a0025e8 bits=16 Vnom=1250, using efuse value 1075
1075
1250 -> optimize_vcore_voltage:efuse 0x4a0025d4 bits=16 Vnom=1250, using efuse value 1109
1109
cor: 1054
do_scale_vcore: volt - 1054 offset_code - 0x3e
IODELAY: IO delay recalibration successfully completed
mpu: 1089
do_scale_vcore: volt - 1089 offset_code - 0x41
mm: 0
gpu: 1075
do_scale_vcore: volt - 1075 offset_code - 0x40
eve: 1075
do_scale_vcore: volt - 1075 offset_code - 0x40
iva: 1109
do_scale_vcore: volt - 1109 offset_code - 0x43
setup_dplls
 core Dpll locked, but not for ideal M = 266,N = 4 values, current values are M = 532,N= 9Core DPLL configured
 per Dpll locked, but not for ideal M = 96,N = 4 values, current values are M = 1920,N= 朗I丏PLL locked
 mpu Dpll locked, but not for ideal M = 500,N = 9 values, current values are M = 1470,N= 24MPU DPLL locked
 >>>>> JYT: sdram_init start------ 
>>sdram_init()
in_sdram = 0
>>>>>JYT: DRA762/752 dmm- else----- 
>>do_sdram_init() 4c000000
>>>>>JYT: DRA752 else case1------ 
>>>>>JYT: DRA752 emif1 752------ 
HW leveling success
<<do_sdram_init() 4c000000
>>do_sdram_init() 4d000000
>>>>>JYT: DRA752 else case1------ 
>>>>>JYT: DRA752 emif1 752------ 
Leveling timeout on EMIF2
<<do_sdram_init() 4d000000
SDRAM: identified size not same as expected size identified: 80 expected: 40000000
<<sdram_init()
 >>>>> JYT: sdram_init completed!------
  • Hi,

    there is an Application Note for EMIF configuration on DRA7xx devices:
    www.ti.com/.../spraca1.pdf

    can you go thru it and see if you can configure your setup?

    Regards,
    Yordan
  • Hi,Yordan

    I have removed the EMIF2  initialization,but the dubug output the error log about "SDRAM size" as follows:

    >>>>> JYT: sdram_init start------

    >>sdram_init()

    in_sdram = 0

    >>>>>JYT: DRA762/752 dmm- else-----

    >>do_sdram_init() 4c000000

    >>>>>JYT: DRA752 else case1------

    >>>>>JYT: DRA752 emif1 752------

    HW leveling success

    <<do_sdram_init() 4c000000

    SDRAM: identified size not same as expected size identified: 80 expected: 40000000

    <<sdram_init()

     >>>>> JYT: sdram_init completed!------

    And I found the dubug is from the file emif-common.c:

    /* Do some testing after the init */
    if (!in_sdram) {
    size_prog = omap_sdram_size();
    size_prog = log_2_n_round_down(size_prog);
    size_prog = (1 << size_prog);

    size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
    size_prog);
    /* Compare with the size programmed */
    if (size_detect != size_prog) {
    printf("SDRAM: identified size not same as expected"
    " size identified: %x expected: %x\n",
    size_detect,
    size_prog);
    } else
    debug("get_ram_size() successful");

    I want to know why SDRAM identified size is not same as expected and what can I  do?

    THANKS!

    Have a good time!

    YOURS

    Yuting

  • Hu Yuting,

    this might happen when DDR timing parameters are not configured properly . I will ping U-boot experts to help with this.

    Regards,
    Yordan
  • Former Member
    0 Former Member in reply to Yordan Kamenov
    Hi,
    Are you trying this software on TI EVM or on Custom board?
    How did you remove EMIF2 configuration? What changes did you do?

    Regards,
    Somnath
  • Former Member
    0 Former Member in reply to Former Member
    Hi,
    Can you provide more detail on this or let us know if you need more information?

    Regards,
    Somnath
  • Former Member
    0 Former Member in reply to Former Member
    Hi,
    Do you need any further help on this? If not, we would close this issue for now.

    Regards,
    Somnath