TMS320C6745 Bootloading from SPI1 flash

Richard,

Yes, you should connect an emulator and read the value in the BOOTCFG register (0x01C1 4020).  This is a read-only register whose value is latched in hardware on the rising edge of reset.  In other words it's not necessary to step through the bootloader code.  Just read back that value.

Let us know how that goes!

Brad

The suggested procedure was attempted.  The boot signals were set for SPI1 flash boot as follows:  BOOT[7]=0,BOOT[3]=1,BOOT[2]=1,BOOT[1]=1,BOOT[0]=0.  The TI Debugger was launched.  When a Target>Connect is attempted, the following error occurs.

Error connecting to the target:

Error 0x80000244/-1178

Fatal Error during: Register, Initialization, OCS,

The target does not have a CPU clock.

Other BOOT settings were then attempted.  BOOT[0] and BOOT[7] could individually be set to 0 and read in the BOOTCFG register, but when both are set to 0, the error occurs.  The clock input to the CPU was verified as being active when RESETn goes high.  There is still no activity on any of the SPI1 signals.  The part number used is TMX320C6745BPTP3.

How did you originally program the SPI flash?  Was this done with the 6745 or did you program the flash before it was populated on the board or some other "pin wiggler"?

Are you using a crystal or an external clock?  Have you verified the clock is stable 100ns prior to releasing reset?

Back to the original question, have you done anything with this device that indicates the device itself is operational and that you don't have an issue with power or clocking?

I have an operational program that I have been running with the emulator for some time.  I used AISgen the and the .out file from this program to create a boot image header file.  I wrote another program to program the flash with this image using the 6745 and the emulator.  I read back the image from the flash and verified it.  I am using a 100MHZ differential PECL clock oscillator which is divided down to 25MHZ and level translated to 1.2V and used as the clock input.

The clock is stable much longer than 100ns before releasing reset.

The program that runs with the emulator uses UART1, the EMIFA asynchronous interface, GPIO and Timer interrupts, so I think the power and clocking is OK.  It also controls two D/As using the same SPI1 as the flash.  I use SPI1_CS[0]n for the flash and GPIO for the D/A chip selects.  All of these functions work using the emulator.

How long after RESETn goes high would the SPI1 flash read start?

Must TRSTn be asserted for boot to work?  I have not looked at this signal at the same time as RESETn.

richard seifert said:

How long after RESETn goes high would the SPI1 flash read start?

We have seen about 390 uS from RESETz high to first SPI clock with a 24 MHz clock input

richard seifert said:

Must TRSTn be asserted for boot to work?  I have not looked at this signal at the same time as RESETn.

In general for power on reset, you want both RESET and TRST low (as shown in the datasheet, Figure 6-4), I believe you should be able to latch the boot pins even if you are initiating  a warm reset (Figure 6-5).

Can you also see what kind of timing you see between RESETz going high to RESETOUT signal going high.

If you say  you have an operation program running in emulator mode, can you also provide the out put of the following debug gel file, running in emulation mode

http://processors.wiki.ti.com/index.php/OMAP-L1x_Debug_Gel_Files

Even though this is an OMAPL1x gel file, it should run fine on your c6745 target. It would've been best if this was run with your boar configured in SPI1 boot mode, but since this currently feasible on your board, let us try to get the output in emulator mode if possible.

Regards

Mukul