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CSL SPI huge delay between successive frames and unwanted loopback

Andreas Weishaupt
Expert 1270 points

Hi.

I'm using the C5515 ezdsp stick and want to setup SPI communication. So far so good, everything compiles and runs and I can monitor SPI_CLK, SPI_TX, SPI_RX and SPI_CS0 on the scope. For TX I transmit a single 16-bit word at once. Seems to work when I look at the scope for SPI_TX but I also see some bits on SPI_RX when I execute SPI_write. The same holds if I execute SPI_read I see something on SPI_TX. How to turn off this behavior? I.e. what I want is SPI_TX=0 while SPI_read is going on and SPI_RX=0 while SPI_write runs. I've looked at the SPI registers and the Loopback bit is disabled all the time while I execute SPI_write and SPI_read. So what's the problem?

The 2nd problem I have is a huge delay between to successive frames for SPI_read. I need to transfer 416 frames of 16-bit "characters" at once. But what I see is not a continuous transfer of 416x16 bits but: after every 16-bits there is no action for about 10us then comes the next 16-bit. How to solve this problem?

My SPI clock frequency is SYS_CLK/8, i.e. 12.5 MHz.

Thanks for all your help

Andreas

 

  • 0
    TI__Expert 8065 points

    Adreas,

    You are observing correct behaviors.

    First: The signal on SPI_RX won't be latched by the clock, so it should not affect the data you want to read. You can ignore it.

    Second: It is a known issue. There is a delay between words. No work around.

    Regards,

    Peter Chung

     

     

  • 0 in reply to Peter Chung
    Expert 1270 points

    Peter,

    Thanks for your answer. W.r.t. to the delay: this is a pity, like that the SPI will not be suited for my application and I will have to do a workaround using another interface. This will be I2S.

    Can you tell me if there are similar problems (delay between words) with I2S on the C5515?

    Target throughput is 64x64x16 bit/800us, i.e. ~80 MByte/s, but in the very very worst case 40 MByte/s would do it.

    Regards,

    Andreas

     

  • 0 in reply to Andreas Weishaupt
    Expert 1270 points

    Ah what I forgot: the "Loopback" I observe on TX while reading is because in SPI_read from CSL, SPIDR1 and SPIDR2 are never set zero. I.e. there should be somewhere the lines

    // clear SPIDAT1 and SPIDAT2
    CSL_SPI_REGS->SPIDR1 = 0x0000,
    CSL_SPI_REGS->SPIDR2 = 0x0000;

    in the while(bufIndex < bufLen) { ... } loop. If we follow the reference guide they should be placed before

    CSL_FINS(CSL_SPI_REGS->SPICMD2, SPI_SPICMD2_CMD, CSL_SPI_SPICMD2_CMD_READ);