Hi,
In the datasheet of AM4376, there is a description of the following timing.
Figure 5-110. QSPI Read Active High Polarity
tsu(D-QSPI_CLK) Setup time, QSPI_D[3:0] valid before active QSPI_CLK edge
min 8.5ns
The QSPI NOR flash(Micron:MT25QL01G) datasheet has the following description.
tCLQV Clock LOW to output valid under 10pF
max 5ns
I checked other SPI NOR flash datasheet, but this value seems to be max 5ns to 9ns.
The timing between falling edge and rising edge of CLK is 10.4ns (48MHz).
Since the DATA output delay time of Flash is Max 5ns, data can not be read correctly in case of AM437x Setup time Min 8.5ns.
CLK half period 10.4ns < DATA output delay time Max 5ns + Setup time min 8.5ns of AM437x
The data in setup time of SPI NOR flash is min 1.75ns.
Comparing the setup time, the spec of AM437x is long, is not it wrong?
Best Regards,
Shigehiro Tsuda
