TDA2PXEVM: about the TDA2PXEVM's flash boot

xu shi

Part Number: TDA2PXEVM
Other Parts Discussed in Thread: SYSBIOS

I want test the TDA2PX's core load, and I use the demo in C:\PROCESSOR_SDK_VISION_03_03_00_00\ti_components\drivers\pdk_01_09_00_17\packages\ti\drv\pm\examples\core_loading.

I have been successfully run the demo in debug mode(directly load the Out file into ram by emulator XDS560),and each core print its own core load message by uart.

The next step is to load the out file into flash. I follow the step about how to make image and write it into flash in TI's docs，and config the SYSboot key into QSPI1 boot mode（I has load the SBL into flash before, and the SBL works good）. After that, I reboot the EVM,but it seems only the A15 core print it core load message and other cores don't work. Pls kindly give some advise about how to resolve the problem. The bellow is the cmd about how to generate the flash image。

:: This file is temporary, used for generating images that are compatible with TI's bootloader
:: This file should be deleted after integrating Valeo's bootloader.

@ECHO OFF

set PATH_TO_VSDK=C:\PROCESSOR_SDK_VISION_03_03_00_00
set OUT2RPRC_TOOL=%PATH_TO_VSDK%\ti_components\drivers\pdk_01_09_00_17\packages\ti\boot\sbl_auto\tools\out2rprc\out2rprc.exe
set MULTICORE_IMG_GEN_TOOL=%PATH_TO_VSDK%\ti_components\drivers\pdk_01_09_00_17\packages\ti\boot\sbl_auto\tools\multicore_image_generator\v1\MulticoreImageGen.exe

echo Converting a15..
call %OUT2RPRC_TOOL% pm_core_loading_app_a15_0_release.xa15fg a15.rprc

echo Converting dsp_1..
call %OUT2RPRC_TOOL% pm_core_loading_app_c66xdsp_1_release.xe66 dsp_1.rprc

echo Converting dsp_2..
call %OUT2RPRC_TOOL% pm_core_loading_app_c66xdsp_2_release.xe66 dsp_2.rprc

echo Converting eve_1..
call %OUT2RPRC_TOOL% pm_core_loading_app_arp32_1_release.xearp32F eve_1.rprc

echo Converting eve_2..
call %OUT2RPRC_TOOL% pm_core_loading_app_arp32_2_release.xearp32F eve_2.rprc

echo Converting m4_0..
call %OUT2RPRC_TOOL% pm_core_loading_app_ipu1_0_release.xem4 m4_0.rprc

echo Converting m4_1..
call %OUT2RPRC_TOOL% pm_core_loading_app_ipu1_1_release.xem4 m4_1.rprc

echo Generating multicore image..
%MULTICORE_IMG_GEN_TOOL% BE 1 AppImage 0 a15.rprc 2 m4_0.rprc 3 m4_1.rprc 8 dsp_1.rprc 9 dsp_2.rprc 10 eve_1.rprc 11 eve_2.rprc

echo Please QSPI BOOT.

over 7 years ago

0 Rishabh Garg over 7 years ago

TI__Guru 55685 points

Hi Xu,

UART is initialized by SBL which is running on A15 and hence you see prints only from A15. Other cores would have loaded and ran the individual application images but you wouldn't have got any prints.
An easier solution would be to have multiple images i.e. one for each core and run with SBL.

Regards,
Rishabh

0 xu shi over 7 years ago in reply to Rishabh Garg

Prodigy 170 points

first ,how to have multiple images ? I mean how to modify the cmd below? Sorry, I'm not familiar with this, can you modify it to me?
echo Generating multicore image..
%MULTICORE_IMG_GEN_TOOL% BE 1 AppImage 0 a15.rprc 2 m4_0.rprc 3 m4_1.rprc 8 dsp_1.rprc 9 dsp_2.rprc 10 eve_1.rprc 11 eve_2.rprc

second, as we know, when there is only one image, the offset is 0x80000，so if there are many images, what is the offset for each image?

third, how to solve my problem if I only accept one image(all core together in one image)? Because multiple images is too complex to burn into flash.

0 Rishabh Garg over 7 years ago in reply to xu shi

TI__Guru 55685 points

Hi Xu,

I meant that have multiple images (one image for one core) and flash one at a time.
In that case command would be like:
%MULTICORE_IMG_GEN_TOOL% BE 1 AppImage 0 a15.rprc for first image
%MULTICORE_IMG_GEN_TOOL% BE 1 AppImage 2 m4_0.rprc for second image

For having one image you need to enhance the application.
You need to use mailboxes to have IPC so that each core can send the data to a master core and master core can control UART and print the core loading data.

Regards,
Rishabh

0 xu shi over 7 years ago in reply to Rishabh Garg

Prodigy 170 points

Hi，Rishabh：
I followed your answer and make 4 images(A15,DSP,EVE,M4), but only the a15 image works, others didn't work. the below is the print message when boot the M4 iamge, and it stop in "Putting MPU in Retention...
" forever, why? Pls kindly give me some advise.
TDA2Px SBL Boot

DPLL Configuration Completed

Clock Domain Configuration Completed

Module Enable Configuration Completed

TI EVM PAD Config Completed

DDR Config Completed

App Image Download Begins

Manufacturer ID - 0x1
Device ID - 0x18
WARNING: Device Id Does not Match

Trying to boot App Image with header version 1

WARNING: Device Id Does not Match

IPU1 CPU0 Image Load Completed

App Image Download Completed

Putting MPU CPU1 in Off mode

EVE MMU configuration completed

EVE MMU configuration completed

*****************************************************************

PMCCNTR counts once every 64 clock cycles, multiple by 64 to get actual CPU cycles

SBL Initial Config Cycles - 104776 (8.94 ms)
SOC Init Cycles - 170600 (14.55 ms)
DDR Config Clock Cycles - 42876 (3.65 ms)
App Image Load Cycles - 370683 (31.63 ms)
Slave Core Bootup Cycles - 131047 (11.18 ms)
SBL Boot-up Cycles - 821045 (70.6 ms)
Time at which SBL started IPU1_0 - 4936 (0.42 ms)
*****************************************************************

Putting MPU in Retention...

0 Rishabh Garg over 7 years ago in reply to xu shi

TI__Guru 55685 points

Hi Xu,

Can you connect to IPU1_0 using CCS and check its state.
Kindly make sure you don't have gels in your target configuration.

Regards,
Rishabh

0 xu shi over 7 years ago in reply to Rishabh Garg

Prodigy 170 points

Hi, Rishabh:

I solved the DSP problem by adding the below code into the DSP's cfg file:

Program.sectMap[".text:_c_int00"] = new Program.SectionSpec();
Program.sectMap[".text:_c_int00"].loadSegment = "DSP1_PROG";
Program.sectMap[".text:_c_int00"].loadAlign = 0x400;

and I solved the M4 problem by add the below code to the M4's cfg file, now only the EVE cores don't work, I guess that it also need to modify the cfg file in PROCESSOR_SDK_VISION_03_03_00_00\ti_components\drivers\pdk_01_09_00_17\packages\ti\drv\pm\examples\core_loading\config\pm_arp32.cfg, but I don't how to do it ,please kindly give me some help.

//the code add for M4's cfg file:

var Program = xdc.useModule('xdc.cfg.Program');
var Cache = xdc.useModule('ti.sysbios.hal.unicache.Cache');
Cache.enableCache = true;

var AMMU = xdc.useModule('ti.sysbios.hal.ammu.AMMU');
AMMU.configureAmmu = true;

/*********************** Medium Pages *************************/

/* ISS */
var entry = AMMU.mediumPages[0];
entry.pageEnabled = AMMU.Enable_YES;
entry.logicalAddress = 0x62200000;
entry.translatedAddress = 0x42200000;
entry.translationEnabled = AMMU.Enable_YES;
entry.size = AMMU.Medium_256K;
entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L1_writePolicy = AMMU.WritePolicy_WRITE_THROUGH;
entry.L1_allocate = AMMU.AllocatePolicy_NON_ALLOCATE;
entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

/* ISS */
var entry = AMMU.mediumPages[1];
entry.pageEnabled = AMMU.Enable_YES;
entry.logicalAddress = 0x62240000;
entry.translatedAddress = 0x42240000;
entry.translationEnabled = AMMU.Enable_YES;
entry.size = AMMU.Medium_256K;
entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L1_writePolicy = AMMU.WritePolicy_WRITE_THROUGH;
entry.L1_allocate = AMMU.AllocatePolicy_NON_ALLOCATE;
entry.L1_posted = AMMU.PostedPolicy_POSTED;
entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

/*********************** Small Pages *************************/

/* EVE1 MBOX0 */
var entry = AMMU.smallPages[2];
entry.pageEnabled = AMMU.Enable_YES;
entry.translationEnabled = AMMU.Enable_YES;
entry.logicalAddress = 0x62088000;
entry.translatedAddress = 0x42088000;
entry.size = AMMU.Small_16K;
entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

/* EVE1 MBOX1 */
var entry = AMMU.smallPages[3];
entry.pageEnabled = AMMU.Enable_YES;
entry.translationEnabled = AMMU.Enable_YES;
entry.logicalAddress = 0x6208C000;
entry.translatedAddress = 0x4208C000;
entry.size = AMMU.Small_16K;
entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

/* EVE2 MBOX0 */
var entry = AMMU.smallPages[4];
entry.pageEnabled = AMMU.Enable_YES;
entry.translationEnabled = AMMU.Enable_YES;
entry.logicalAddress = 0x62188000;
entry.translatedAddress = 0x42188000;
entry.size = AMMU.Small_16K;
entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

/* EVE2 MBOX1 */
var entry = AMMU.smallPages[5];
entry.pageEnabled = AMMU.Enable_YES;
entry.translationEnabled = AMMU.Enable_YES;
entry.logicalAddress = 0x6218C000;
entry.translatedAddress = 0x4218C000;
entry.size = AMMU.Small_16K;
entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

/* System EDMA TPCC */
var entry = AMMU.smallPages[6];
entry.pageEnabled = AMMU.Enable_YES;
entry.translationEnabled = AMMU.Enable_YES;
entry.logicalAddress = 0x63300000;
entry.translatedAddress = 0x43300000;
entry.size = AMMU.Small_16K;
entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

/* System EDMA TPCC */
var entry = AMMU.smallPages[7];
entry.pageEnabled = AMMU.Enable_YES;
entry.translationEnabled = AMMU.Enable_YES;
entry.logicalAddress = 0x63304000;
entry.translatedAddress = 0x43304000;
entry.size = AMMU.Small_16K;
entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

/* System Mailbox 5, 6 */
var entry = AMMU.smallPages[8];
entry.pageEnabled = AMMU.Enable_YES;
entry.translationEnabled = AMMU.Enable_YES;
entry.logicalAddress = 0x68840000;
entry.translatedAddress = 0x48840000;
entry.size = AMMU.Small_16K;
entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

/* System Mailbox 7, 8 */
var entry = AMMU.smallPages[9];
entry.pageEnabled = AMMU.Enable_YES;
entry.translationEnabled = AMMU.Enable_YES;
entry.logicalAddress = 0x68844000;
entry.translatedAddress = 0x48844000;
entry.size = AMMU.Small_16K;
entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

/*********************** Large Pages *************************/
var entry = AMMU.largePages[0];
entry.pageEnabled = AMMU.Enable_YES;
entry.translationEnabled = AMMU.Enable_YES;
entry.logicalAddress = 0x40000000;
entry.translatedAddress = 0x40000000;
entry.size = AMMU.Large_512M;
entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

/* map program code/data memory into ammu (cacheable) */
var entry = AMMU.largePages[1];
entry.pageEnabled = AMMU.Enable_YES;
entry.translationEnabled = AMMU.Enable_YES;
entry.logicalAddress = 0x80000000;
entry.translatedAddress = 0x80000000;
entry.size = AMMU.Large_512M;
entry.L1_cacheable = AMMU.CachePolicy_CACHEABLE;
entry.L1_posted = AMMU.PostedPolicy_POSTED;
entry.L1_allocate = AMMU.AllocatePolicy_ALLOCATE;
entry.L1_writePolicy = AMMU.WritePolicy_WRITE_BACK;
entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

/* map SR_0 data memory into ammu (non-cacheable) */
var entry = AMMU.largePages[2];
entry.pageEnabled = AMMU.Enable_YES;
entry.translationEnabled = AMMU.Enable_YES;
entry.logicalAddress = 0xA0000000;
entry.translatedAddress = 0x80000000;
entry.size = AMMU.Large_512M;
entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

0 Rishabh Garg over 7 years ago in reply to xu shi

TI__Guru 55685 points

Hi Xu,

I have asked EVE experts to comment on this.

Regards,
Rishabh

0 Piyali Goswami over 7 years ago in reply to Rishabh Garg

TI__Mastermind 30245 points

Hi Xu,

You would not be able to set the EVE MMU from the CFG file. This needs to be done in the code. For the specific example, you need to make the following changes to make the EVE example to boot from SBL: (The convention used is + is in the beginning of the line if the lines need to be added, - is in the beginning if the line needs to be removed). Kindly note the fix for this would be available in the next SDK release.

File: examples/core_loading/config/pm_arp32.cfg

+/***********************************************
+ * Reset Module Configuraion *
+ ***********************************************/
+var Reset = xdc.useModule('xdc.runtime.Reset');
+Reset.fxns[Reset.fxns.length++] = "&eveCommonMmuConfig";
+
+

if (CurrentCore == "arp32_1")
{
Program.sectMap[".vecs"] = "EVE1_VECS_MEM";
- Program.sectMap["ttbSection"] = "EVE1_DATA_MEM";
+ Program.sectMap[".ttbSection"] = new Program.SectionSpec();
+ Program.sectMap[".ttbSection"].loadSegment = "EVE1_DATA_MEM";
+ Program.sectMap[".ttbSection"].type = "NOINIT";
}
if (CurrentCore == "arp32_2")
{
Program.sectMap[".vecs"] = "EVE2_VECS_MEM";
- Program.sectMap["ttbSection"] = "EVE2_DATA_MEM";
+ Program.sectMap[".ttbSection"] = "EVE2_DATA_MEM";
+ Program.sectMap[".ttbSection"].type = "NOINIT";
}
if (CurrentCore == "arp32_3")
{
Program.sectMap[".vecs"] = "EVE3_VECS_MEM";
- Program.sectMap["ttbSection"] = "EVE3_DATA_MEM";
+ Program.sectMap[".ttbSection"] = "EVE3_DATA_MEM";
+ Program.sectMap[".ttbSection"].type = "NOINIT";
}
if (CurrentCore == "arp32_4")
{
Program.sectMap[".vecs"] = "EVE4_VECS_MEM";
- Program.sectMap["ttbSection"] = "EVE4_DATA_MEM";
+ Program.sectMap[".ttbSection"] = "EVE4_DATA_MEM";
+ Program.sectMap[".ttbSection"].type = "NOINIT";
}

File: examples/core_loading/src/core_loading.c

-#if defined (BUILD_ARP32)
- eveCommonMmuConfig(SOC_EVE_MMU0_BASE);
-#endif

tskPrms.stack = gLoadAppTskStackMain;
tskPrms.stackSize = sizeof (gLoadAppTskStackMain);
tskPrms.arg0 = (UArg) NULL;
- task = Task_create(loadCoreTask, NULL, &eb);
+ task = Task_create(loadCoreTask, &tskPrms, &eb);

File: examples/core_loading/src/tlb_config_eve_common.c

-#pragma DATA_SECTION(gTtbAddress, "ttbSection")
+#pragma DATA_SECTION(gTtbAddress, ".ttbSection")
UInt32 gTtbAddress[3072U];

-void eveCommonMmuConfig(UInt32 baseAddr)
+void eveCommonMmuConfig()
{
UInt32 i, numTlbEntries;
MMU_TlbEntry_t tlbEntry;
-
+ UInt32 baseAddr = SOC_EVE_MMU0_BASE;
UInt32 j;

File: examples/core_loading/src/tlb_config_eve_common.h

-void eveCommonMmuConfig(UInt32 baseAddr);
+void eveCommonMmuConfig(void);

Thanks and Regards,

Piyali

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TDA2PXEVM: about the TDA2PXEVM's flash boot