c6455 srio NWRITE_R packets & interrrupt

Hi, Now I am working with c6455 SRIO, I have two questions:
1.If master write a NWRITE_R packets to slave, when the master receive the response, does it mean that the slave has moved the data to its L2 RAM with EDMA?
2.In the master write slave transaction, how can the slave CPU knows that the data has been writen to its L2 RAM? In spru976c, it describes as follows:
   To avoid this condition, all data transfers from the peripheral through the DMA use write-with-response DMA bus commands, allowing the peripheral to always be aware that outstanding transfers have completed. Interrupts are generated only after all DMA bus responses are received.
   Is the above description means that the slave CPU services interrupt after the data EDMA'd to its L2 RAM? Can the slave generate an interrupt to CPU to indicate the data has moved to L2 RAM? and How to set the interrupt?