We have a design that has a unique booting scheme. Right now, we are only using the ARM side of the DaVinci. But, we are looking at the possiblity of using the DSP side for some of our image processing needs to offload the ARM (some examples of this would be appreciated, by the way). Our board contains six DaVinci DM6446 processors. One is the master and the other 5 are slaves. The master processor boots from NAND flash into DDR2 RAM. The other processors are set to boot via HPI and the master copies the main program directly into DDR2 memory on the slaves. My question is this. Can the slave processors then boot their DSPs from DDR2 memory since they don't contain FLASH or other EMIF device using the DSPBOOTADDR register?