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C55x Memory Map

BDavisSwRI
Prodigy 50 points


I have been developing on a client provided custom board with a C5510A.  At my request the client replaced the 8Mbit flash with a 32 Mbit flash.  Now CCS4 reports the following when I try to load my target:

C55xx_0: File Loader: Data verification failed at address 0x00800002 Please verify target memory and memory map.

Error found during data verification.

Ensure the linker command file matches the memory map.

 

I presumed this would leave my base address the same and only change my length from 0x100000 to 0x400000.  The only place I know to modify this is in the .TCF file via the Configuration Tool UI

The generated MAP file reports the following:

MEMORY CONFIGURATION

 

         name            origin    length      used     unused   attr    fill

                        (bytes)   (bytes)    (bytes)   (bytes)

----------------------  --------  ---------  --------  --------  ----  --------

  VECT                  00000200   00000100  00000100  00000000  RWIX

  DARAM                 00000300   0000fd00  0000e498  00001868  RWIX

  SARAM1                00010000   00010000  0000a052  00005fae  RWIX

  SARAM                 00020000   00020000  00000942  0001f6be  RWIX

  SARAM2                00040000   0000ff00  0000ff00  00000000  RWIX

  SDRAM1                00800000   00800000  000ae05e  00751fa2  RWIX

 

What I would really like is concise documentation on memory mapping WRT custom boards, available tools and best practices.

Also, is there an automated tool for cleaning up the TCF file?  It looks like every mod I have ever made is still in there.

Finally, Once I have this flash functional I want to load my HEX file and boot from it.  My client was using a high price corelis product to do this but my FPGA IDEs have always provided integrated tools for this.  Does CCS4 have some such tool?

Cheers,

Benjamin

  • 0
    TI__Guru**** 162655 points

    Benjamin,

    CCS does not come with a tool integrated for external flash programming.  There was a company working on one but I am not sure if they have finished: http://www.softwaredesignsolutions.com/

    You can view the memory map of the debugger from the tools menu when you are in a debug session, it will be defined in the start GEL file which can also be accessed from the Tools menu.

    I will move the thread into the BIOS forum so you get get help on the tcf questions.  But we might have to move it into the C55x forum afterwards.

    Regards,

    John

  • 0
    TI__Mastermind 37985 points

    Benjamin,
    there is no an automated tool for cleaning up TCF scripts. But, it's just a text file, so you can remove statements that you know are redundant in any text editor. Then, you open the new TCF script in Gconf and you end up with an equivalent configuration but a shorter script. This assumes you correctly identified redundant statements. 

    That being said, there is a cdb2tcf tool that converts old BIOS 4.xx configurations to BIOS 5 configurations. That tool can be tricked into converting a BIOS 5 configuration to a BIOS 5 configuration, where the generated TCF script ends up being shorter than the initial script. However, the tool was never tested to do that, and would be worth using for such purposes only if you have many scripts that need cleaning, and you can easily recognize that the generated script is really equivalent to the initial configuration.

    As for the memory map, the TCF script is where you would make memory map changes that are then propagated to the linker command file used to build the app.

    Sasha

  • 0 in reply to Sasha Slijepcevic
    Prodigy 50 points

    OK, regarding the memory mapping, Can you direct me to a concise document regarding the custom boards and their configuration?  Can you theorize as to why the larger flash would corrupt my memory map?

     

    My CEn signals have been double checked and the 32 Mbit size of the new flash fits within the mappable space of a single CE.  CE0 maps to my local resources (RAMs, GrayChip, FPGA, etc), CE1 maps to my now upgraded flash chip (same mfg, package, etc, just more bits.  Address lines for the additional bits were always present), CE 2 is routed to my 64Mbit SDRAM and CE3 is not connected per TI documentation regarding external SDRAM chips of this size.

     

    Is there anything I may be missing that the new flash could cause a side effect with?   Do I need to do some manual "cleaning" of any file(s) that do not get properly reset after a hardware change?

     

    Any clues are appreciated.

  • 0 in reply to BDavisSwRI
    TI__Mastermind 37985 points

    I am not sure what kind of documentation for custom boards are you looking for? I can only speak about the Tconf side of the build. When you build a configuration, you start from some initial platform, and the initial memory platforms are listed in Appendix B of the Tconf User's Guide (SPRU007). Then, you make changes in your TCF script to get the memory map that corresponds to what you have on the board, but Tconf can't verify what you have on the board or what is in the start GEL file defined in CCS.

    My guess is that those two memory maps do not match, and you have to adjust either you TCF script of the GEL file to get the right memory map. Changing the map in the TCF script is something you already did I guess, but just in case, here is an example how you would change the size of SDRAM.

    bios.MEM.instance("SDRAM").len = 0x400000;

    As for changing the memory map in CCS, I hope someone more familiar with that will answer. I don't really know all conditions under which CCS would complain about the memory map.