• State TI Thinks Resolved
  • Locked Locked
  • Replies 8 replies
  • Answers 3 answers
  • Subscribers 98 subscribers
  • Views 1046 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

RTOS/TMS320C6678: PCIe configuration for C6678

Noufal P
Intellectual 920 points

Part Number: TMS320C6678

Tool/software: TI-RTOS

Hi 

I have a custom board with c6678 DSP and Kintex7 FPGA. Both will communicate through PCIe. I have gone through PCIe example where both RC and EP are DSPs. But in my case DSP is RC and FPGA is EP.

So, for configuring PCIe on my board, can i use example code as it is or should i do any extra configuration for EP?

Regards,

Noufal P 

  • 0
    TI__Guru 65405 points
    Ho Noufal,

    The SW team is notified. They will post their feedback directly here.

    BR
    Tsvetolin Shulev
  • 0 in reply to Cvetolin Shulev-XID
    TI__Guru* 95265 points
    Hi,

    Please use the latest Processor SDK RTOS 4.3 for C6678 device and the PCIE test example, the DSP side the code configure itself as RC, you may setup lane speed and lane width according to the FPGA side. Also, the code doesn't do the enumeration process, this is typically done by an operating system. The RC side enables the link training. Your FPGA side also need to have the similar setup as DSP, but as EP.

    Regards, Eric
  • 0 in reply to lding
    Intellectual 920 points
    Hi, Thanks for your immediate reply.
    In my case, FPGA side there is no OS running. So enumeration will not happen. So I can do the remote configuration for EP side from RC right?
    And am not aware about what and all registers of EP to be configured remotely from RC.
  • 0 in reply to Noufal P
    Guru 13202 points

    Hello!

    Yes, you have to configure FPGA remotely from DSP. Beware, some features like MSI have different layout in config space, so you can't use PCIe LLD directly.

  • 0 in reply to Victor Kazmirenko
    TI__Guru* 95265 points
    Hi,

    At least you need something in the EP side to enable the linking training, then you can have PCIE link coming up for the RC sees into EP side. Then you can do some configuration of the EP from RC side.

    Regards, Eric
  • 0 in reply to lding
    Intellectual 920 points

    hi sir,

    That means after configuring RC side, i have to wait for link to become up (pcieWaitLinkUp-function as used in example code). Then can i follow the EP side configuration provided in example code or something different since enumeration is not happening at EP side?

    lding said:
    Hi,

      Then you can do some configuration of the EP from RC side.


    Can you please tell me what are those configuration of EP done by RC mentioned by you?

    Regards,

    Noufal P

  • 0 in reply to Noufal P
    Guru 13202 points

    Noufal P said:
    Can you please tell me what are those configuration of EP done by RC mentioned by you?

    Hello!

    We setup RC closely what was in example, then after waiting for link up we set lane_skew.ackDisable and lane_skew.fcDisable to match those set for RC, and then configure remote EP, which at minimum requires setting of remote BARs. You may use LLD example by simply changing 

    barCfg.location = pcie_LOCATION_REMOTE;

    In our setup most of the setup is related with bus mastering and MSI features. You may skip it at this stage.

    Hope this helps.

  • 0 in reply to Victor Kazmirenko
    Intellectual 920 points
    Hi sir,

    I will check and update you

    Thanks
    Noufal P