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Base address for NAND CS3 space in DM365

AlanZhang
Intellectual 515 points

Hi,

I am trying to figure out the base address for NAND flash device on our DM365 based board. The information is needed for CONFIG_SYS_NAND_BASE_LIST in U-Boot compilation.

In our board, the NAND flash chip enable pin is connected to AM_CE1 pin.

According to "2.6 Memory Map Summary" in DM365 datasheet (SPRS457C), the AEMIF Data (CE1) is mapped to 0x04000000, while CE0 is mapped to 0x02000000.

However, as I look at the davinci_dm365_evm.h in both u-boot and Linux kernel drivers, the base address for CE1 is CONFIG_SYS_NAND_BASE+0x4000, which is 0x02004000.

That confused me: how DM365 chip is selecting CE1 and CE0 pins? Are they selected based on the address value given, or based on the value set on NANDFCR register?

What base address should I used for AM_CE1 (or CS3 space in AEMIF SPRUFI1C document)?

Thanks

Alan

  • 0
    TI__Genius 9490 points

    Alan,

    CS0(CS3 labled in SPRUFI1C) : 0x02000000

    CS1(CS3 labled in SPRUFI1C): 0x04000000

    If the davinci_dm365_evm.h file in uboot/linux defines the beginning of their CSx space with an offset that is left to the user (there might be a reason they are not touching the lower 0x4000 addresses so that's ok) the AEMIF CSx space is architected in the AEMIF controller in DM365 as I clarified above.

    regards,

    miguel

     

  • 0 in reply to Miguel A. Alanis
    Intellectual 515 points

    miguel:

    Thanks for reply. 

    May I clarify my understanding on chip selection pin functions. Do you mean whenever data is read/write to 0x02000000 address space, AM_CE0 will be asserted; and whenever to 0x04000000, AM_CE1 will be asserted?

    In other words, data read/write to 0x02004000 (the address used in davinci_dm365_evm.h for second NAND flash chip) will assert AM_CE0 pin, NOT  AM_CE1 pin. 

    Is my understanding correct?

    Alan