RTOS/EVMK2H: RTOS GIC, CpIntc, INTC, HAL, AINTC Usage

Alfredo Sepulveda

Part Number: EVMK2H
Other Parts Discussed in Thread: SYSBIOS, 66AK2H14

Tool/software: TI-RTOS

Hello everyone,

I was trying to use the Hwi to link up a GPIO/SPI event using the ARMCore Pac. There's a guide on how to do this using the DSP's but i'm mainly interested in using the ARM. SysBios includes documentation describing the API.

I've looked up the GIC module and I looked at the technical reference guide but I am still confused between what libraries I should use to accomplish this. I want to accomplish this at runtime. So here are my Questions/ comments

How do i enable these events so that the GIC will pick up on them and let the ARM CPU's handle them not the DSP's?

Looking at the CIC controller diagram, 4 exist on this SoC. There are 480 Shared Peripherial Events that the AINTC listens to, including 36 that come from CIC2.I get lost in the documentation when it comes to the system events, and Interrupts and which module handles what.

I know what event numbers correspond tothe peripherials but i don't know how to map them in the event combiner to trigger a specific interrupt, it looks like the event combiner is specific to the DSP's. There's a Dispatcher mentioned in the SYSBIOS APin the CpIntc module but i'm not sure how to use it.

Also there's a parameter I don't understand in one of the API Descriptions

Function: Cpintc_dispatch(Uint Sysint, Cpintc_funcPtr fxn, UArg arg, Bool unmask)

The Parameter in question is the UArg arg, the others are self explanitaory but this one remains ambiguous to me, its also used in other functions, like the timer. what is this supposed to represent / how is it used, all the api mentions is "Argument to Function", what can this value be?

How does the Dispatcher link the Hwi Module?

Does servicing the Event from a particular peripherial service that Interrupt? EX: XEVT_SPI is triggered, does the system get interrupted, or just a flag is set?

I would like some clarification on this please, also an example / psudocode would be awesome, apologies for my rambling i just have a lot of questions.

over 7 years ago

0 lding over 7 years ago

TI__Guru* 95265 points

Hi,

You may install the Processor SDK RTOS 4.3 release for K2H. There is GPIO driver example on ARM to toggle LED under pdk_k2hk_4_0_x\packages\ti\drv\gpio\. The code GPIO_setCallback() registered the ISR, you can trace back how it worked.

Regards, Eric

0 Alfredo Sepulveda over 7 years ago in reply to lding

Intellectual 790 points

Thanks for the reply, I looked at how the exampled did all of this, but i still need some help with the HWAttrs

There are several events that can be intitialized in the GPIO_v0_Attrs.IntCfg

The documentation of the structure only mentions the that this is the vector number, and when i try to use the structure in the code more than one attribute is shown

In my code:
//Declare cfg variable
GPIO_v0_Attrs gpio_cfg;
// The Structure shows more than one field i can use settings for
gpio_cfg.intCfg->EventID
gpio_cfg.intCfg->Int#
gpio_cfg.intCfg->IntcMuxinEvent
gpio_cfg.intCfg->Intcmux#
gpio_cfg.intCfg->IntcMuxOutEvent

Where can i look up these parameters?
What do the different event numbers mean?

on a side note...If i wanted to use a different core other than core 0 or more than one core how would these settings change / what api's would be helpful?

0 lding over 7 years ago in reply to Alfredo Sepulveda

TI__Guru* 95265 points

Hi,

Keystone devices (including K2H) uses V0 GPIO driver. Sitara devices uses V1 GPIO driver.

The definition of this is inside gpio\src\v0\gpio_v0.h:

typedef struct GPIO_IntCfg_s {
/*! DSP: int vector number; ARM: GIC int number (peripheral event ID + 32) */
uint32_t intNum;
/* CorePac specific Event ID, input to CorePac interrupt controller */
uint32_t eventId;
/* intc mux number, Keystone inc mux is Chip Interrupt Controller
if assigned -1, system resource manager will decide the mux num */
int32_t intcMuxNum;
/* intc mux input event ID, for Keystone, it is the input event to CIC
if assigned -1, system resource manager will decide the mux input event ID */
int32_t intcMuxInEvent;
/* intc mux output event ID, for Keystone, it is the Host interrupt num
if assigned -1, system resource manager will decide the mux output event ID */
int32_t intcMuxOutEvent;

} GPIO_IntCfg;

The usage of this is: gpio\soc\k2h\gpio_soc.c, you can see 32 entries like:

/* GPIO port 0 pin 1 */
{
#ifdef _TMS320C6X
OSAL_REGINT_INTVEC_EVENT_COMBINER,
CSL_C66X_COREPAC_GPIO_INTN, /* DSP corePac GPIO pin 1 interrupt event for Core 1 */
#else
CSL_ARM_GIC_GPIO_INT1 + 32,
0,
#endif
INVALID_INTC_MUX_NUM,
0,
0
},
/* GPIO port 0 pin 2 */
{
#ifdef _TMS320C6X
OSAL_REGINT_INTVEC_EVENT_COMBINER,
CSL_C66X_COREPAC_GPIO_INTN, /* DSP corePac GPIO pin 2 interrupt event for Core 2 */
#else
CSL_ARM_GIC_GPIO_INT2 + 32,
0,
#endif
INVALID_INTC_MUX_NUM,
0,
0
},

So, for ARM there are 32 GPIO interrupt, each with a definition of:
CSL_ARM_GIC_GPIO_INTx + 32,
0,
0xFFFF,
0,
0

The intNum you can find out from 66AK2H14 data sheet Table 8-23. System Event Mapping — ARM CorePac Interrupts (120 to 151). The code setup the interrupt is gpio\soc\v0\gpio_v0.c.

If you run Linux on ARM, there is SMP support on Linux so all 4 cores are used. For the RTOS, all the tests we used the first ARM core. There may be SMP supports from SYSBIOS: processors.wiki.ti.com/.../BIOS. The same interrupt code should work on core 1 as well, but we didn't try.

Regards, Eric

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RTOS/EVMK2H: RTOS GIC, CpIntc, INTC, HAL, AINTC Usage