Linux/AM3354: Interrupt preemption

Nancy Wang

Part Number: AM3354

Tool/software: Linux

Hi team,

The customer wants to realize Interrupt Preemption in linux. But he failed. Please help to provide demo about nested interrupt and kindly point out the key procedures.

over 7 years ago

0 RonB over 7 years ago

TI__Mastermind 30746 points

Nancy,

Can you please provide more information? What did the customer try that failed?

Do they want to enable HW Interrupt Preemption? Usually, in LInux the HW IRQ is kept very small and work is deferred to another kernel thread like a work queue, tasklet, or softirq. This is safer and less complex. These threads can then be prioritized properly.

Why do they feel like they need preemption? More information about he problem or use case would help us provide the best alternatives.

Thanks for the post.

0 YueLei Zhang over 7 years ago in reply to RonB

Prodigy 40 points

Hi:

First of all, thank you for your helps.

Our equipment needs frequent interruptions, I use the kernel version is 3.2.0,and I use the rt-patch version is patch-3.2-rt10.patch.

Under these conditions:

I test the Interrupt latency is about 10us to 60us. However, our equipment need the minimum interrupt interval is about 90us.and the interrupt count is continuous up to 2200(I call this interrupt A) , during these interrupts ,sometimes we need to transmission data by net 、 serial port(I call this interrupt B).

now ,I use gpio3 to deal the interrupt A. if the program is dealing with the interrupt B, the interrupt A maybe lost. so I need to open the Interrupt Preemption function ,and set the interrupt A priority higher than interrupt B.

I do some change in the kernel ,but I failured.

static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs)
{
u32 irqnr,cpsr1,cpsr2,cpsr3,cpsr4;
u32 proprity,threshold,testasm;
unsigned long old ,temp;
do {
omap_intc_save_context_addr(base_addr);       //step1 & 2

  irqnr = readl_relaxed(base_addr + 0x98);
  if (irqnr)
   goto out;

  irqnr = readl_relaxed(base_addr + 0xb8);
  if (irqnr)
   goto out;

irqnr = readl_relaxed(base_addr + 0xd8);

out:
if (!irqnr)
break;

  irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET); //step4
  irqnr &= ACTIVEIRQ_MASK;

  if (irqnr){
   if((irqnr == 62) || (irqnr == 93) || (irqnr == 94))
   {
    proprity = readl_relaxed(base_addr + 0x60);     //step3
    writel(proprity, base_addr + INTC_THRESHOLD);      //step3
    //threshold = readl_relaxed(base_addr + INTC_THRESHOLD);
    //printk("**irqnumber = %d proprity = %d threshold = %d\r\n",irqnr, proprity,threshold);

    writel(0x1, base_addr + INTC_CONTROL);   //step 5
    barrier();   //step 6


    __asm__ __volatile__ (
     "mrs %0, cpsr\n"
     :"r=" (cpsr1)
     );

    if((irqnr == 62) || (irqnr == 93) || (irqnr == 94))
     irq_enable();   //step 7

    __asm__ __volatile__ (
     "mrs %0, cpsr\n"
     :"r=" (cpsr2)
     );
    if((irqnr == 93) || (irqnr == 94))
     printk("###cpsr1 = 0x%x,cpsr2 = 0x%x\r\n",cpsr1,cpsr2);
   }

   handle_IRQ(irqnr, regs);

   /*if((irqnr == 93) || (irqnr == 94))
    irq_disable();*/

   omap_intc_restore_context_addr(base_addr);
  }
} while (irqnr);
}

asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs)
{
void __iomem *base_addr = OMAP3_IRQ_BASE;
omap_intc_handle_irq(base_addr, regs);
}

I need some demo about

Fullscreen irq.c Download

/*
 * linux/arch/arm/mach-omap2/irq.c
 *
 * Interrupt handler for OMAP2 boards.
 *
 * Copyright (C) 2005 Nokia Corporation
 * Author: Paul Mundt <paul.mundt@nokia.com>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/exception.h>
#include <asm/mach/irq.h>


/* selected INTC register offsets */

#define INTC_REVISION		0x0000
#define INTC_SYSCONFIG		0x0010
#define INTC_SYSSTATUS		0x0014
#define INTC_SIR		0x0040
#define INTC_CONTROL		0x0048
#define INTC_PROTECTION		0x004C
#define INTC_IDLE		0x0050
#define INTC_THRESHOLD		0x0068
#define INTC_MIR0		0x0084
#define INTC_MIR_CLEAR0		0x0088
#define INTC_MIR_SET0		0x008c
#define INTC_PENDING_IRQ0	0x0098
#define INTC_ILR0           0x0100

/* Number of IRQ state bits in each MIR register */
#define IRQ_BITS_PER_REG	32


#define OMAP2_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
#define OMAP3_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
#define INTCPS_SIR_IRQ_OFFSET	0x0040	/* omap2/3 active interrupt offset */
#define ACTIVEIRQ_MASK		0x7f	/* omap2/3 active interrupt bits */

/*
 * OMAP2 has a number of different interrupt controllers, each interrupt
 * controller is identified as its own "bank". Register definitions are
 * fairly consistent for each bank, but not all registers are implemented
 * for each bank.. when in doubt, consult the TRM.
 */
static struct omap_irq_bank {
	void __iomem *base_reg;
	unsigned int nr_irqs;
} __attribute__ ((aligned(4))) irq_banks[] = {
	{
		/* MPU INTC */
		.nr_irqs	= 96,
	},
};

/* Structure to save interrupt controller context */
struct omap3_intc_regs {
	u32 sysconfig;
	u32 protection;
	u32 idle;
	u32 threshold;
	u32 ilr[INTCPS_NR_IRQS];
	u32 mir[INTCPS_NR_MIR_REGS];
};

/* INTC bank register get/set */

static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
{
	__raw_writel(val, bank->base_reg + reg);
}

static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
{
	return __raw_readl(bank->base_reg + reg);
}

/* XXX: FIQ and additional INTC support (only MPU at the moment) */
static void omap_ack_irq(struct irq_data *d)
{
	intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
}

static void omap_mask_ack_irq(struct irq_data *d)
{
	irq_gc_mask_disable_reg(d);
	omap_ack_irq(d);
}

static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
{
	unsigned long tmp;

	tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
	printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
			 "(revision %ld.%ld) with %d interrupts\n",
			 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);

	tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
	tmp |= 1 << 1;	/* soft reset */
	intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);

	while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
		/* Wait for reset to complete */;

	/* Enable autoidle */
	intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
	
	intc_bank_write_reg(100, bank, INTC_THRESHOLD);  	   //INTC_THRESHOLD


	intc_bank_write_reg(4 << 2, bank, INTC_ILR0 + 62*4);   //gpio3
	intc_bank_write_reg(6 << 2, bank, INTC_ILR0 + 63*4);   //gpio3

	intc_bank_write_reg(8 << 2, bank, INTC_ILR0 + 93*4);   //eth
	intc_bank_write_reg(8 << 2, bank, INTC_ILR0 + 94*4);   //eth

	intc_bank_write_reg(16 << 2, bank, INTC_ILR0 + 68*4);  //timer
	
	intc_bank_write_reg(12 << 2, bank, INTC_ILR0 + 73*4);  //uart1

	intc_bank_write_reg(14 << 2, bank, INTC_ILR0 + 72*4);  //uart0

	tmp = intc_bank_read_reg(bank, INTC_THRESHOLD) & 0xff;

	printk(KERN_INFO "**************INTC_THRESHOLD = %d \r\n",tmp);
}

int omap_irq_pending(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
		struct omap_irq_bank *bank = irq_banks + i;
		int irq;

		for (irq = 0; irq < bank->nr_irqs; irq += 32)
			if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 +
					       ((irq >> 5) << 5)))
				return 1;
	}
	return 0;
}

static __init void
omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;

	gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
					handle_level_irq);
	ct = gc->chip_types;
	ct->chip.irq_ack = omap_mask_ack_irq;
	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;

	ct->regs.ack = INTC_CONTROL;
	ct->regs.enable = INTC_MIR_CLEAR0;
	ct->regs.disable = INTC_MIR_SET0;
	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
				IRQ_NOREQUEST | IRQ_NOPROBE, 0);
}

static void __init omap_init_irq(u32 base, int nr_irqs)
{
	void __iomem *omap_irq_base;
	unsigned long nr_of_irqs = 0;
	unsigned int nr_banks = 0;
	int i, j;

	omap_irq_base = ioremap(base, SZ_4K);
	if (WARN_ON(!omap_irq_base))
		return;

	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
		struct omap_irq_bank *bank = irq_banks + i;

		bank->nr_irqs = nr_irqs;

		/* Static mapping, never released */
		bank->base_reg = ioremap(base, SZ_4K);
		if (!bank->base_reg) {
			printk(KERN_ERR "Could not ioremap irq bank%i\n", i);
			continue;
		}

		omap_irq_bank_init_one(bank);

		for (j = 0; j < bank->nr_irqs; j += 32)
			omap_alloc_gc(bank->base_reg + j, j, 32);

		nr_of_irqs += bank->nr_irqs;
		nr_banks++;
	}

	printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
	       nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
}

void __init omap2_init_irq(void)
{
	omap_init_irq(OMAP24XX_IC_BASE, 96);
}

void __init omap3_init_irq(void)
{
	omap_init_irq(OMAP34XX_IC_BASE, 96);
}

void __init ti81xx_init_irq(void)
{
	omap_init_irq(OMAP34XX_IC_BASE, 128);
}
static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];

void omap_intc_save_context(void)
{
	int ind = 0, i = 0;
	printk("&&&&&&&&&&&&&&&&&save\r\n");
	for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
		struct omap_irq_bank *bank = irq_banks + ind;
		intc_context[ind].sysconfig =
			intc_bank_read_reg(bank, INTC_SYSCONFIG);
		intc_context[ind].protection =
			intc_bank_read_reg(bank, INTC_PROTECTION);
		intc_context[ind].idle =
			intc_bank_read_reg(bank, INTC_IDLE);
		intc_context[ind].threshold =
			intc_bank_read_reg(bank, INTC_THRESHOLD);
		for (i = 0; i < INTCPS_NR_IRQS; i++)
			intc_context[ind].ilr[i] =
				intc_bank_read_reg(bank, (0x100 + 0x4*i));
		for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
			intc_context[ind].mir[i] =
				intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +
				(0x20 * i));
	}
}
void omap_intc_save_context_addr(void __iomem *base_addr)
{
	int ind = 0, i = 0;

	intc_context[0].sysconfig = readl_relaxed(base_addr + INTC_SYSCONFIG);
	intc_context[0].protection =readl_relaxed(base_addr + INTC_PROTECTION);
	intc_context[0].idle = readl_relaxed(base_addr + INTC_IDLE);
	intc_context[0].threshold = readl_relaxed(base_addr + INTC_THRESHOLD);
	
	intc_context[0].ilr[62] = readl_relaxed(base_addr + (0x100 + 0x4*62));
	intc_context[0].ilr[63] = readl_relaxed(base_addr + (0x100 + 0x4*63));
	intc_context[0].ilr[93] = readl_relaxed(base_addr + (0x100 + 0x4*93));
	intc_context[0].ilr[94] = readl_relaxed(base_addr + (0x100 + 0x4*94));
	/*intc_context[0].ilr[68] = readl_relaxed(base_addr + (0x100 + 0x4*68));
	intc_context[0].ilr[72] = readl_relaxed(base_addr + (0x100 + 0x4*72));
	intc_context[0].ilr[73] = readl_relaxed(base_addr + (0x100 + 0x4*73));*/
	
	/*for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
		intc_context[0].mir[i] = readl_relaxed(base_addr + INTC_MIR0 + (0x20 * i));*/
}

void omap_intc_restore_context(void)
{
	int ind = 0, i = 0;
	printk("&&&&&&&&&&&&&&&&&restore\r\n");

	for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
		struct omap_irq_bank *bank = irq_banks + ind;
		intc_bank_write_reg(intc_context[ind].sysconfig,
					bank, INTC_SYSCONFIG);
		intc_bank_write_reg(intc_context[ind].sysconfig,
					bank, INTC_SYSCONFIG);
		intc_bank_write_reg(intc_context[ind].protection,
					bank, INTC_PROTECTION);
		intc_bank_write_reg(intc_context[ind].idle,
					bank, INTC_IDLE);
		intc_bank_write_reg(intc_context[ind].threshold,
					bank, INTC_THRESHOLD);
		for (i = 0; i < INTCPS_NR_IRQS; i++)
			intc_bank_write_reg(intc_context[ind].ilr[i],
				bank, (0x100 + 0x4*i));
		for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
			intc_bank_write_reg(intc_context[ind].mir[i],
				 &irq_banks[0], INTC_MIR0 + (0x20 * i));
	}
	/* MIRs are saved and restore with other PRCM registers */
}
void omap_intc_restore_context_addr(void __iomem *base_addr)
{
	int ind = 0, i = 0;

	writel(intc_context[0].sysconfig, base_addr + INTC_SYSCONFIG);
	writel(intc_context[0].sysconfig, base_addr + INTC_SYSCONFIG);
	writel(intc_context[0].protection, base_addr + INTC_PROTECTION);
	writel(intc_context[0].idle, base_addr + INTC_IDLE);
	writel(intc_context[0].threshold, base_addr + INTC_THRESHOLD);

	writel(intc_context[0].ilr[62], base_addr + (0x100 + 0x4*62));
	writel(intc_context[0].ilr[63], base_addr + (0x100 + 0x4*63));
	writel(intc_context[0].ilr[93], base_addr + (0x100 + 0x4*93));
	writel(intc_context[0].ilr[94], base_addr + (0x100 + 0x4*94));
	/*writel(intc_context[0].ilr[68], base_addr + (0x100 + 0x4*68));
	writel(intc_context[0].ilr[72], base_addr + (0x100 + 0x4*72));
	writel(intc_context[0].ilr[73], base_addr + (0x100 + 0x4*73));*/


	
	/*for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
		writel(intc_context[0].mir[i], base_addr + INTC_MIR0 + (0x20 * i));*/
	/* MIRs are saved and restore with other PRCM registers */
}
/*
 * Enable IRQs
 */
static inline void irq_enable(void)
{
	unsigned long temp;
	asm volatile(
		"	mrs	%0, cpsr	@ arch_local_irq_enable\n"
		"	bic	%0, %0, #128\n"
		"	msr	cpsr_c, %0"
		: "=r" (temp)
		:
		: "memory", "cc");

			/*__asm__ __volatile__(
				"mrs %0, cpsr\n" 
				"bic %1, %0, #0x80\n" 
				"msr cpsr, %1\n" 
				: "=r" (old), "=r" (temp) 
				: 
				: "memory"); */
}

/*
 * Disable IRQs
 */
static inline void irq_disable(void)
{
	unsigned long temp;
	asm volatile(
		"	mrs	%0, cpsr	@ arch_local_irq_disable\n"
		"	orr	%0, %0, #128\n"
		"	msr	cpsr_c, %0"
		: "=r" (temp)
		:
		: "memory", "cc");
}

static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs)
{
	u32 irqnr,cpsr1,cpsr2,cpsr3,cpsr4;
	u32 proprity,threshold,testasm;
	unsigned long old ,temp;
	do {
		//omap_intc_save_context_addr(base_addr);    			//step1 & 2   zyl
		
		irqnr = readl_relaxed(base_addr + 0x98);
		if (irqnr)
			goto out;

		irqnr = readl_relaxed(base_addr + 0xb8);
		if (irqnr)
			goto out;

		irqnr = readl_relaxed(base_addr + 0xd8);

out:
		if (!irqnr)
			break;

		irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);  //step4
		irqnr &= ACTIVEIRQ_MASK;
		
		if (irqnr){
			if((irqnr == 62) || (irqnr == 93) || (irqnr == 94))
			{
				proprity = readl_relaxed(base_addr + 0x60);   		//step3  zyl
				writel(proprity, base_addr + INTC_THRESHOLD);  	    //step3  zyl
				//threshold = readl_relaxed(base_addr + INTC_THRESHOLD);
				//printk("**irqnumber = %d  proprity = %d  threshold = %d\r\n",irqnr, proprity,threshold);
			
				writel(0x1, base_addr + INTC_CONTROL);   //step 5 zyl
				barrier();   //step 6 zyl
				
		
				__asm__ __volatile__ (
					"mrs	%0, cpsr\n"
					:"r=" (cpsr1)
					);
				if((irqnr == 62) || (irqnr == 93) || (irqnr == 94))
					irq_enable();
			

				__asm__ __volatile__ (
					"mrs	%0, cpsr\n"
					:"r=" (cpsr2)
					);
				if((irqnr == 93) || (irqnr == 94))
					printk("###cpsr1 = 0x%x,cpsr2 = 0x%x\r\n",cpsr1,cpsr2);
			}
	
			handle_IRQ(irqnr, regs);

			/*if((irqnr == 93) || (irqnr == 94))
				irq_disable();*/
			
			omap_intc_restore_context_addr(base_addr);
		}
	} while (irqnr);
}

asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs)
{
	void __iomem *base_addr = OMAP2_IRQ_BASE;
	omap_intc_handle_irq(base_addr, regs);
}

#ifdef CONFIG_ARCH_OMAP3

void omap3_intc_suspend(void)
{
	/* A pending interrupt would prevent OMAP from entering suspend */
	omap_ack_irq(0);
}

void omap3_intc_prepare_idle(void)
{
	/*
	 * Disable autoidle as it can stall interrupt controller,
	 * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
	 */
	intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
}

void omap3_intc_resume_idle(void)
{
	/* Re-enable autoidle */
	intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
}
//zyl uxe this
asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs)
{
	void __iomem *base_addr = OMAP3_IRQ_BASE;
	omap_intc_handle_irq(base_addr, regs);
}
#endif /* CONFIG_ARCH_OMAP3 */

.thank you

0 RonB over 7 years ago in reply to YueLei Zhang

TI__Mastermind 30746 points

Thank you for the good overview of what you are trying to achieve.

user5328339 said:
I do some change in the kernel ,but I failured.

Can you please expand on what is failing? Are you still missing interrupt A? Or, are you having some other trouble.

One thing that I notice is the printf statement. This will add significant latency to your irq and could easily lead to

We don't typically recommend modifying interrupt handlers like this. However, it may be necessary to achieve your very specific goal. Have you tried priorities at the application level like something I recommended earlier? You could set the priority of the work for interrupt A at a very high priority and interrupt B lower and this might achieve the same goal you were looking for.

0 YueLei Zhang over 7 years ago in reply to RonB

Prodigy 40 points

HI:

During the interrupt A continuous incoming, if I want to send a file(about 100kb) by internet(this also use interrupt, interrupt B), the interrupt A will missing one or two count out of 1000 .

the printk function will print message at some free time, because I use the rt-patch .

now the interrupt A priority is 4, and the interrupt B priority is 10.

last time , Nancy give us a intc.c:

AM335X PROCESSOR_SDK_RTOS_04.03.00.05\pdk_am335x_1_0_10\packages\ti\starterware\soc\am335x\intc.c

Download address：http://www.ti.com.cn/tool/cn/processor-sdk-am335x

due to the different version of kernel. I cant use intc.c directly. but the basic principle is similar.The only difference is in intc.c :

/*
     * Enable IRQ and switch to system mode. Interrupt Service Routines will
     * execute in System Mode, so that nested interrupts can be handled.
     * Save user mode LR.
     */
    asm("    push    {r7}\n\t"
        "    mrs     r7, CPSR\n\t"
        "    orr     r7, r7, #0x1F\n\t"
        "    bic     r7, r7, #0x80\n\t"
        "    msr     CPSR, r7\n\t"
        "    STMFD   r13!, {r14}");

    /* Call the respective interrupt handler call back function */
    pIntrHandlers[activeIntrId](activeIntrId, cpuId,
                                                pUserParameter[activeIntrId]);

    /*
     * Disable IRQ and change back to IRQ mode.
     * Restore user mode LR.
     */
    asm("    LDMFD    r13!, {r14}\n\t"
        "    CPSID    i, 0x12\n\t"
        "    pop      {r7}");

/* Reload original priority threshold value */
HW_WR_REG32((SOC_AINTC_REGS + INTC_THRESHOLD), prevPriMask);

it I use this program ,the kernel will boot failure.

I use :

irq_enable:

asm volatile(
  " mrs %0, cpsr @ arch_local_irq_enable\n"
  " bic %0, %0, #128\n"
  " msr cpsr_c, %0"
  : "=r" (temp)
  :
  : "memory", "cc");

irq_disable:

unsigned long temp;
asm volatile(
  " mrs %0, cpsr @ arch_local_irq_disable\n"
  " orr %0, %0, #128\n"
  " msr cpsr_c, %0\n"
  : "=r" (temp)
  :
  : "memory", "cc");

my program only change cpsr register, not enter the system mode, because the kernel will boot failure.

do you have some other demo to open interrupt preemption function?

Is there any problem in this irq.c?:

Fullscreen 4617.irq.c Download

/*
 * linux/arch/arm/mach-omap2/irq.c
 *
 * Interrupt handler for OMAP2 boards.
 *
 * Copyright (C) 2005 Nokia Corporation
 * Author: Paul Mundt <paul.mundt@nokia.com>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/exception.h>
#include <asm/mach/irq.h>


/* selected INTC register offsets */

#define INTC_REVISION		0x0000
#define INTC_SYSCONFIG		0x0010
#define INTC_SYSSTATUS		0x0014
#define INTC_SIR		0x0040
#define INTC_CONTROL		0x0048
#define INTC_PROTECTION		0x004C
#define INTC_IDLE		0x0050
#define INTC_THRESHOLD		0x0068
#define INTC_MIR0		0x0084
#define INTC_MIR_CLEAR0		0x0088
#define INTC_MIR_SET0		0x008c
#define INTC_PENDING_IRQ0	0x0098
#define INTC_ILR0           0x0100

/* Number of IRQ state bits in each MIR register */
#define IRQ_BITS_PER_REG	32


#define OMAP2_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
#define OMAP3_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
#define INTCPS_SIR_IRQ_OFFSET	0x0040	/* omap2/3 active interrupt offset */
#define ACTIVEIRQ_MASK		0x7f	/* omap2/3 active interrupt bits */



/*
 * OMAP2 has a number of different interrupt controllers, each interrupt
 * controller is identified as its own "bank". Register definitions are
 * fairly consistent for each bank, but not all registers are implemented
 * for each bank.. when in doubt, consult the TRM.
 */
static struct omap_irq_bank {
	void __iomem *base_reg;
	unsigned int nr_irqs;
} __attribute__ ((aligned(4))) irq_banks[] = {
	{
		/* MPU INTC */
		.nr_irqs	= 96,
	},
};

/* Structure to save interrupt controller context */
struct omap3_intc_regs {
	u32 sysconfig;
	u32 protection;
	u32 idle;
	u32 threshold;
	u32 ilr[INTCPS_NR_IRQS];
	u32 mir[INTCPS_NR_MIR_REGS];
};

/* INTC bank register get/set */

static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
{
	__raw_writel(val, bank->base_reg + reg);
}

static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
{
	return __raw_readl(bank->base_reg + reg);
}

/* XXX: FIQ and additional INTC support (only MPU at the moment) */
static void omap_ack_irq(struct irq_data *d)
{
	intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
}

static void omap_mask_ack_irq(struct irq_data *d)
{
	irq_gc_mask_disable_reg(d);
	omap_ack_irq(d);
}

static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
{
	unsigned long tmp;

	tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
	printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
			 "(revision %ld.%ld) with %d interrupts\n",
			 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);

	tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
	tmp |= 1 << 1;	/* soft reset */
	intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);

	while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
		/* Wait for reset to complete */;

	/* Enable autoidle */
	intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
	
	intc_bank_write_reg(20, bank, INTC_THRESHOLD);  	   //INTC_THRESHOLD


	intc_bank_write_reg(4 << 2, bank, INTC_ILR0 + 62*4);   //gpio3
	intc_bank_write_reg(6 << 2, bank, INTC_ILR0 + 32*4);   //gpio2

	intc_bank_write_reg(10 << 2, bank, INTC_ILR0 + 93*4);   //eth
	intc_bank_write_reg(10 << 2, bank, INTC_ILR0 + 94*4);   //eth

	intc_bank_write_reg(12 << 2, bank, INTC_ILR0 + 68*4);  //timer  open this ,system fault

	intc_bank_write_reg(8 << 2, bank, INTC_ILR0 + 73*4);  //uart1  --pc


	tmp = intc_bank_read_reg(bank, INTC_THRESHOLD) & 0xff;

	printk(KERN_INFO "**************INTC_THRESHOLD = %d \r\n",tmp);
}

int omap_irq_pending(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
		struct omap_irq_bank *bank = irq_banks + i;
		int irq;

		for (irq = 0; irq < bank->nr_irqs; irq += 32)
			if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 +
					       ((irq >> 5) << 5)))
				return 1;
	}
	return 0;
}

static __init void
omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;

	gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
					handle_level_irq);
	ct = gc->chip_types;
	ct->chip.irq_ack = omap_mask_ack_irq;
	ct->chip.irq_mask = irq_gc_mask_disable_reg;
	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;

	ct->regs.ack = INTC_CONTROL;
	ct->regs.enable = INTC_MIR_CLEAR0;
	ct->regs.disable = INTC_MIR_SET0;
	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
				IRQ_NOREQUEST | IRQ_NOPROBE, 0);
}

static void __init omap_init_irq(u32 base, int nr_irqs)
{
	void __iomem *omap_irq_base;
	unsigned long nr_of_irqs = 0;
	unsigned int nr_banks = 0;
	int i, j;

	omap_irq_base = ioremap(base, SZ_4K);
	if (WARN_ON(!omap_irq_base))
		return;

	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
		struct omap_irq_bank *bank = irq_banks + i;

		bank->nr_irqs = nr_irqs;

		/* Static mapping, never released */
		bank->base_reg = ioremap(base, SZ_4K);
		if (!bank->base_reg) {
			printk(KERN_ERR "Could not ioremap irq bank%i\n", i);
			continue;
		}

		omap_irq_bank_init_one(bank);

		for (j = 0; j < bank->nr_irqs; j += 32)
			omap_alloc_gc(bank->base_reg + j, j, 32);

		nr_of_irqs += bank->nr_irqs;
		nr_banks++;
	}

	printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
	       nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
}

void __init omap2_init_irq(void)
{
	omap_init_irq(OMAP24XX_IC_BASE, 96);
}

void __init omap3_init_irq(void)
{
	omap_init_irq(OMAP34XX_IC_BASE, 96);
}

void __init ti81xx_init_irq(void)
{
	omap_init_irq(OMAP34XX_IC_BASE, 128);
}
static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];

void omap_intc_save_context(void)
{
	int ind = 0, i = 0;
	printk("&&&&&&&&&&&&&&&&&save\r\n");
	for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
		struct omap_irq_bank *bank = irq_banks + ind;
		intc_context[ind].sysconfig =
			intc_bank_read_reg(bank, INTC_SYSCONFIG);
		intc_context[ind].protection =
			intc_bank_read_reg(bank, INTC_PROTECTION);
		intc_context[ind].idle =
			intc_bank_read_reg(bank, INTC_IDLE);
		intc_context[ind].threshold =
			intc_bank_read_reg(bank, INTC_THRESHOLD);
		for (i = 0; i < INTCPS_NR_IRQS; i++)
			intc_context[ind].ilr[i] =
				intc_bank_read_reg(bank, (0x100 + 0x4*i));
		for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
			intc_context[ind].mir[i] =
				intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +
				(0x20 * i));
	}
}
void omap_intc_save_context_addr(void __iomem *base_addr)
{
	intc_context[0].sysconfig = readl_relaxed(base_addr + INTC_SYSCONFIG);
	intc_context[0].protection =readl_relaxed(base_addr + INTC_PROTECTION);
	intc_context[0].idle = readl_relaxed(base_addr + INTC_IDLE);
	//intc_context[0].threshold = readl_relaxed(base_addr + INTC_THRESHOLD);
	//printk("rrr****intc_context[0].threshold = %d\r\n",intc_context[0].threshold);
	/*intc_context[0].ilr[62] = readl_relaxed(base_addr + (0x100 + 0x4*62));
	intc_context[0].ilr[63] = readl_relaxed(base_addr + (0x100 + 0x4*63));
	intc_context[0].ilr[93] = readl_relaxed(base_addr + (0x100 + 0x4*93));
	intc_context[0].ilr[94] = readl_relaxed(base_addr + (0x100 + 0x4*94));
	intc_context[0].ilr[68] = readl_relaxed(base_addr + (0x100 + 0x4*68));
	intc_context[0].ilr[72] = readl_relaxed(base_addr + (0x100 + 0x4*72));
	intc_context[0].ilr[73] = readl_relaxed(base_addr + (0x100 + 0x4*73));*/
	
	/*for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
		intc_context[0].mir[i] = readl_relaxed(base_addr + INTC_MIR0 + (0x20 * i));*/
}

void omap_intc_restore_context(void)
{
	int ind = 0, i = 0;
	printk("&&&&&&&&&&&&&&&&&restore\r\n");

	for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
		struct omap_irq_bank *bank = irq_banks + ind;
		intc_bank_write_reg(intc_context[ind].sysconfig,
					bank, INTC_SYSCONFIG);
		intc_bank_write_reg(intc_context[ind].sysconfig,
					bank, INTC_SYSCONFIG);
		intc_bank_write_reg(intc_context[ind].protection,
					bank, INTC_PROTECTION);
		intc_bank_write_reg(intc_context[ind].idle,
					bank, INTC_IDLE);
		intc_bank_write_reg(intc_context[ind].threshold,
					bank, INTC_THRESHOLD);
		for (i = 0; i < INTCPS_NR_IRQS; i++)
			intc_bank_write_reg(intc_context[ind].ilr[i],
				bank, (0x100 + 0x4*i));
		for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
			intc_bank_write_reg(intc_context[ind].mir[i],
				 &irq_banks[0], INTC_MIR0 + (0x20 * i));
	}
	/* MIRs are saved and restore with other PRCM registers */
}
void omap_intc_restore_context_addr(void __iomem *base_addr)
{
	writel(20, base_addr + INTC_THRESHOLD);

	writel(intc_context[0].sysconfig, base_addr + INTC_SYSCONFIG);
	writel(intc_context[0].protection, base_addr + INTC_PROTECTION);
	writel(intc_context[0].idle, base_addr + INTC_IDLE);
	
//printk("****intc_context[0].threshold = %d\r\n",intc_context[0].threshold);
	/*writel(intc_context[0].ilr[62], base_addr + (0x100 + 0x4*62));
	writel(intc_context[0].ilr[63], base_addr + (0x100 + 0x4*63));
	writel(intc_context[0].ilr[93], base_addr + (0x100 + 0x4*93));
	writel(intc_context[0].ilr[94], base_addr + (0x100 + 0x4*94));
	writel(intc_context[0].ilr[68], base_addr + (0x100 + 0x4*68));
	writel(intc_context[0].ilr[72], base_addr + (0x100 + 0x4*72));
	writel(intc_context[0].ilr[73], base_addr + (0x100 + 0x4*73));*/


	
	/*for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
		writel(intc_context[0].mir[i], base_addr + INTC_MIR0 + (0x20 * i));*/
	/* MIRs are saved and restore with other PRCM registers */
}
/*
 * Enable IRQs
 */
static inline void irq_enable(void)
{
	/*asm("	 push	 {r7}\n\t"
		"	 mrs	 r7, CPSR\n\t"
		"    orr     r7, r7, #0x1F\n\t"
		"	 bic	 r7, r7, #0x80\n\t"
		"	 msr	 CPSR, r7\n\t"
		"	 STMFD	 r13!, {r14}");
*/
	unsigned long temp,cpsr1;
	asm volatile(
		"	mrs	%0, cpsr	@ arch_local_irq_enable\n"
		"	bic	%0, %0, #128\n"
		"	msr	cpsr_c, %0"
		: "=r" (temp)
		:
		: "memory", "cc");


}

/*
 * Disable IRQs
 */
static inline void irq_disable(void)
{
	unsigned long temp;
	asm volatile(
		"	mrs	%0, cpsr	@ arch_local_irq_disable\n"
		"	orr	%0, %0, #128\n"
		"	msr	cpsr_c, %0\n"
		: "=r" (temp)
		:
		: "memory", "cc");
		/*
	asm("    LDMFD    r13!, {r14}\n\t"
        "    CPSID    i, 0x12\n\t"
        "    pop      {r7}");*/
}


volatile int preemptiveflag = 0;
volatile int lastirqn = 0;
volatile int lastproprity = 0;

static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs)
{
	u32 irqnr;
	u32 proprity,threshold,testasm;
	unsigned long old ,temp;
	
	do {
		irqnr = readl_relaxed(base_addr + 0x98);
		if (irqnr)
			goto out;

		irqnr = readl_relaxed(base_addr + 0xb8);
		if (irqnr)
			goto out;

		irqnr = readl_relaxed(base_addr + 0xd8);
		if (irqnr)
			goto out;

		irqnr = readl_relaxed(base_addr + 0xf8);

out:

		if (!irqnr)
			break;
		
		omap_intc_save_context_addr(base_addr); 				    //step1 & 2   zyl
			
		proprity = readl_relaxed(base_addr + 0x60);					
		writel(proprity, base_addr + INTC_THRESHOLD); 				//step3  zyl

		irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);   //step4
		irqnr &= ACTIVEIRQ_MASK;
		
		if (irqnr){
			//if(preemptiveflag == 1)
				//printk("*****kernel preemptive  last=%d  now=%d  lastp=%d  nowp=%d**********\r\n",lastirqn, irqnr,lastproprity,proprity );

			writel(0x1, base_addr + INTC_CONTROL);   			//step 5 zyl
			barrier();   										//step 6 zyl
			
			if((irqnr == 93) || (irqnr == 94) || (irqnr == 73) || (irqnr == 32)) 
				irq_enable();								    //step 7 zyl
			
			preemptiveflag = 1;                                 //start to handle interrupt zyl
			lastirqn = irqnr;
			lastproprity = proprity;
			handle_IRQ(irqnr, regs);
			
			if((irqnr == 93) || (irqnr == 94) || (irqnr == 73) || (irqnr == 32)) 
				irq_disable();

			omap_intc_restore_context_addr(base_addr);
			preemptiveflag = 0;                                 //handle over zyl

		}
		else
			printk("@@@@@@@@@@@@@@unkonw irq\r\n");
	} while (irqnr);

	/*
	if(flag == 0){
		printk("********omap_ack_irq**********\r\n");
		omap_ack_irq(NULL);
	}*/
}

asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs)
{
	void __iomem *base_addr = OMAP2_IRQ_BASE;
	omap_intc_handle_irq(base_addr, regs);
}

#ifdef CONFIG_ARCH_OMAP3

void omap3_intc_suspend(void)
{
	/* A pending interrupt would prevent OMAP from entering suspend */
	omap_ack_irq(0);
}

void omap3_intc_prepare_idle(void)
{
	/*
	 * Disable autoidle as it can stall interrupt controller,
	 * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
	 */
	intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
}

void omap3_intc_resume_idle(void)
{
	/* Re-enable autoidle */
	intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
}
//zyl use this
asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs)
{
	void __iomem *base_addr = OMAP3_IRQ_BASE;

	
	omap_intc_handle_irq(base_addr, regs);
}
#endif /* CONFIG_ARCH_OMAP3 */

0 Schuyler Patton over 7 years ago in reply to YueLei Zhang

TI__Mastermind 40750 points

Hi,

For interrupt A what is the time frame of how often that interrupt happens? Is the time value deterministic? You mentioned that the interrupt works continuously up to 2200, is this a time unit? What is interrupt A frequency?

Could describe how often Interrupt A is triggered? The source of this interrupt is gpio 3. What does this interrupt represent?
Could describe how often Interrupt B is triggered? The source of this interrupt is it serial or Ethernet?

How did you measure interrupt latency? Please describe the process of measurement.
Have you been using cyclictest to measure system latency?

This link here is to a website that measures the system latency of the Beagle Bone Black which is showing about 128uS system latency on an example system. This value is greater than 90uS you mentioned as a requirement for your project. Depending on system loading you may get different numbers, could be worse or better, it will depend on the requirements for your application.

www.osadl.org/Latency-plot-of-system-in-rack-7-slot.qa-latencyplot-r7s8.0.html

For RT Pre-empt systems interrupts are converted to threads that can be managed by scheduling policy and priority. The recommendation would be to experiment with Interrupt A and Interrupt B as application threads rather than trying to modify the interrupt handler to re-enable interrupts.

Best Regards,
Schuyler

0 YueLei Zhang over 7 years ago in reply to Schuyler Patton

Prodigy 40 points

Hi :

The frequency of interrupt is about 120us, I use gpio3-21 as the interrupt source. and use this interrupt to send data to fpga.

IRQ_EINT2 = gpio_to_irq(GPIO_TO_PIN(3, 21));

If I want to check the data, I need to use Ethernet(interrupt B). Interrupt A and B maybe happens at the same time.

I measure interrupt latency by oscilloscope, most of the latency is less than 20us.

how to experiment with Interrupt A and Interrupt B as application threads?

you mean the Pre-empt cant solve the problem?

0 Schuyler Patton over 7 years ago in reply to YueLei Zhang

TI__Mastermind 40750 points

Hi,

To find out if Pre-empt can solve problem you will have to create an experiment like previously mentioned. Are you are familiar with the cyclictest application? This code is open source and the suggestion I have is to take that code and modify it by changing it from using a timer to using the gpio to emulate the Interrupt A that you are trying to do. This test will help you determine if you will be able to hit your Interrupt A latency requirements in a statistical manner. Currently TI does not have an example on how to do the change from the timer to a GPIO but I imagine there are examples on how to block on a gpio on the web.

Best Regards,
Schuyler

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Linux/AM3354: Interrupt preemption