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HECC bit timing of AM3157 is extended at ERM=1(Edge Resynchronization Mode)

RY9983
Guru 10570 points
Other Parts Discussed in Thread: AM3517


Hello.
I have encountered problem that HECC bit timing is extended at ERM=1.
I confirmed it on AM3517EVM which just connect #2pin and #3pin of J36 on the application board.
And I used AM35xx BSL and test program which can download in the Logic PD site.
  - 1013707A_AM35xx_BSL.zip\bsl\lib\evmam35xx_bsl.lib
  - 1013707A_AM35xx_BSL.zip\tests\evm\can

Because default bit rate is 0.8125MHz in test program, pulse width represents 1.23usec in ERM=0.
But, it changes into 1.38usec when I set ERM=1.

Because bit timing delay exceeds receiver acceptable timing by environment effects, I am really embarrassed.
Could you help me please?

1) Does the HECC adjust rising edge time of the transmit data at ERM=1?

2) Please teach me if there are something restriction about this.

3) Or, I would like to clarify this problem is never happen at ERM=0.

Best Regards,
BL.HSR-WZ

  • 0
    TI__Prodigy 670 points

    Hi,

    I am looking at it and will get back to you soon.

    Regards,
    Chintan

  • 0
    TI__Prodigy 670 points

    Hello BL.HSR-WZ,

    If you check section 23.6.1 of the TRM, it talks about the different time segments in the nominal bit time and one of the segments is Phase Segment, which leghthens or shortens depending on the edge phase error when resynchronization is selected. The lenghtening or shortening depends on the Synchroniztion Jump width which are bits 8 and 9 of CANBTC register. The value of these bits is 0 and from the explanation provided in the TRM, it is evident that SJWcalc=SJWBTC+1, so we get SJWcalc=1 Time Quantum. Now from section 23.6.2, we see that Bit Time in Time Quanta is 8 when ERM=0. For ERM=1, Phase_seg1 grows by SJW (which is 1 TQ) and hence the Bit Time is now 9TQ. If you calculate the Bit Rate with this Bit Time, you get Bit Rate = 26M / (4*9) = 722.22 Mbits/s which corresponds to a pulse width of 1.385usec which is what you get.

    Regards,
    Chintan

  • 0 in reply to Chintan Gala
    Guru 10570 points


    Hello Chintan

    I really appreciate your support.

    Best Regards,
    RY

  • 0 in reply to RY9983
    TI__Prodigy 670 points

    Not a problem.

    Regards,

    Chintan

  • 0 in reply to Chintan Gala
    Guru 10570 points

    Hello Chintan

    Could you help me again, please?

    Since the CAN protocol usually synchronize on only falling edge,
    the ERM function is not CAN protocol.
    When do I use ERM function?
    I would like to know the purpose of ERM function.

    Best Regards,
    RY

  • 0 in reply to RY9983
    TI__Prodigy 670 points

    When you enable the ERM bit, the CAN module synchronizes on both rising and falling edges.

    Regards,
    Chintan

  • 0 in reply to Chintan Gala
    Guru 10570 points

    Chintan, Thanks so much for your help.
    Best regards, RY

     

  • 0 in reply to RY9983
    Guru 10570 points

    Hello Chintan.

    I had feed back from my customer.
    I think that Edge Resynchronization Mode(ERM=1) is original mode of TI.
    When I adjust bit timing using CANBTC.SJW field at ERM=1, AM3517 succeed in the data transfer.
    But, when AM3517 is receiver, the bit timing is shortened and AM3517 fails receiving at ERM=1.

    How do you think about this?
    How can I use ERM appropriately?

    Best regards,
    RY

  • 0 in reply to RY9983
    TI__Prodigy 670 points

    Yes, ERM is TI's functionality.
    So are you saying that even after manipulating the SJW value, AM3517 fails receiving the data? Because shortened bit timing should be taken care by SJW value.

    Regards,
    Chintan

  • 0 in reply to Chintan Gala
    Guru 10570 points

    Hello Chintan,
    Yes, the AM3517 fails when it is receiving the data.

    The reception fails because 1TQ expands only as for Bit Timing of the transmission when ERM is set.
    Is it correct operation?

    Best regards,
    RY

  • 0 in reply to RY9983
    TI__Prodigy 670 points

    Hello RY,

    I am a bit confused. Are the timings being extended or shortened, because earlier you said shortened. Also who is transmitting the data? Are you saying that the transmitter's bit timings are extended by 1TQ and at the receiver you find shortened bit timings? Did you change SJW value at receiver AM3517? Can you please provide as much details as possible explaining the complete scenario?

    Thanks & Regards,
    Chintan

  • 0 in reply to RY9983
    TI__Prodigy 670 points

    RY,

    I had a question. Why is the customer setting ERM? What is he trying to do?


    Thanks
    Chintan

  • 0 in reply to RY9983
    TI__Prodigy 670 points

    RY,

    May I know how did you check if the reception fails? Can you explain the hardware set up and procedure? I found AM3517 to be working as a receiver even with ERM=1.

    Regards,
    Chintan

  • 0 in reply to Chintan Gala
    Guru 10570 points

    Hello Chintan
    I appreciate your help.
    I would like to answer about your questions.

     - Are the timings being extended or shortened, because earlier you said shortened.
       Also who is transmitting the data?
       --> When AM3517 is transmitter, the bit timing is extended on ERM=1.
           To make transmitting succeed, I have decreased the bit timing by SJW.
           After that, the bit timing is not enough when AM3517 is receiver.

           The transmitter changes by the time. (AM3517, other CAN module ..)

     - Are you saying that the transmitter's bit timings are extended by 1TQ and at the
       receiver you find shortened bit timings?
       --> Yes, I am.

     - Did you change SJW value at receiver AM3517?
       --> No, I did not.
           I set SJW only once.

     - I had a question. Why is the customer setting ERM? What is he trying to do?
       --> They think that if ERM improve the quality of the communication,
           they would like to use the function.

     - May I know how did you check if the reception fails?
       --> They are using original target board of AM3517.
           But, you may check the reception fail using two AM3517EVMs.
           One AM3517 set ERM=1, and the other set ERM=0.
           You can use BSL test code which can get on Logic PD web site.

         - 1013707A_AM35xx_BSL.zip\bsl\lib\evmam35xx_bsl.lib
         - 1013707A_AM35xx_BSL.zip\tests\evm\can

     - Can you explain the hardware set up and procedure?
       --> You should connect J36[3:2] to other J36[3:2] on AM3517 application board.

    I hope you solve this problem.

    Thank you in advance.
    Best regards,
    RY

  • 0 in reply to RY9983
    TI__Prodigy 670 points

    It seems your hardware set up is not correct. Check out http://processors.wiki.ti.com/index.php/Sitara_AM35x_CAN_(HECC)_Linux_Driver#EVM_Information for hardware set up. Also, how did you use BSL test to check funcionality between two EVM boards because the test sends 4 bytes from one board, waits for ACKS and then expects the other board to send data. In our case, the other board won't send any data and so the test would fail. However, if the sender receives ACKS and starts acting as receiver, then even if the test fails, effectively it means that the transmission at sender and reception at receiver was successful. This is how I tested with h/w setup as mentioned in the link above and it worked for different combinations of ERM at sender and receiver without programming SJW.

    Regards,
    Chintan