TMDXEVM8148: Adding TVP5147, i2c write / read issue

/*
 *
 * Framebuffer device registration for TI TI816x platforms
 *
 * Copyright (C) 2009 Texas Instruments Inc.
 * Author: Yihe Hu <yihehu@ti.com>
 *
 * Some code and ideas taken from TI OMAP2 Platforms
 * by Tomi Valkeinen.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/bootmem.h>
#include <linux/io.h>
#include <linux/vps_capture.h>
#include <linux/ti81xxfb.h>
#include <linux/ti81xx.h>
#include <mach/hardware.h>
#include <mach/board-ti814x.h>
#include <mach/board-ti816x.h>
#include <asm/mach/map.h>


#if defined(CONFIG_TI81XX_VPSS) || defined(CONFIG_TI81XX_VPSS_MODULE)

static u64 ti81xx_dma_mask = ~(u32)0;
static struct platform_device vpss_device = {
	.name = "vpss",
	.id = -1,
	.dev = {
		.platform_data = NULL,
	},
};
static struct vps_platform_data vps_pdata;


static int __init ti81xx_vpss_init(void)
{
	/*FIXME add platform data here*/
	int r;
	if (cpu_is_ti816x() || cpu_is_dm385()) {
		if (cpu_is_dm385())
			vps_pdata.cpu = CPU_DM813X;
		else
			vps_pdata.cpu = CPU_DM816X;
		vps_pdata.numvencs = 4;
		vps_pdata.vencmask = (1 << VPS_DC_MAX_VENC) - 1;
	} else if (cpu_is_ti814x()) {
		vps_pdata.cpu = CPU_DM814X;
		vps_pdata.numvencs = 3;
		vps_pdata.vencmask = (1 << VPS_DC_MAX_VENC) - 1 \
					- VPS_DC_VENC_HDCOMP;
	}

	vpss_device.dev.platform_data = &vps_pdata;
	r = platform_device_register(&vpss_device);
	if (r)
		printk(KERN_ERR "unable to register ti81xx_vpss device\n");
	else
		printk(KERN_INFO "registered ti81xx_vpss device\n");
	return r;
}

#if defined(CONFIG_TI81XX_HDMI_MODULE) || defined(CONFIG_TI81XX_HDMI)

static struct platform_device ti81xx_hdmi_plat_device = {
	.name = "TI81XX_HDMI",
	.id = -1,
	.num_resources = 0,
	.dev = {
		/*.release = ti81xx_hdmi_platform_release,*/
		.platform_data = NULL,
	}
};

static int __init ti81xx_hdmi_init(void)
{
	int r;
	/*FIXME add platform data here*/
	r = platform_device_register(&ti81xx_hdmi_plat_device);
	if (r)
		printk(KERN_ERR "Unable to register ti81xx onchip-HDMI device\n");
	else
		printk(KERN_INFO "registered ti81xx on-chip HDMI device\n");
	return r;
}
#else
static int __init ti81xx_hdmi_init(void)
{
	return 0;
}
#endif

#if defined(CONFIG_VIDEO_TI81XX_VIDIN_MODULE) || \
		defined(CONFIG_VIDEO_TI81XX_VIDIN)

#define HDVPSS_CAPTURE_INST0_BASE	0x48105500
#define HDVPSS_CAPTURE_INST0_SIZE	1024u

#define HDVPSS_CAPTURE_INST2_BASE	0x48105A00
#define HDVPSS_CAPTURE_INST2_SIZE	1024u
u8 ti81xx_card_name[] = "TI81xx_catalogue";
struct ti81xxvin_interface tvp7002_pdata = {
	.clk_polarity = 0,
	.hs_polarity = 0,
	.vs_polarity = 1,
	.fid_polarity = 0,
	.sog_polarity = 0,

};
struct ti81xxvin_interface tvp514x_pdata = {
	.clk_polarity = 0,
	.hs_polarity = 0,
	.vs_polarity = 1,
	.fid_polarity = 0,
	.sog_polarity = 0,

};
static struct ti81xxvin_subdev_info hdvpss_capture_sdev_info[] = {
#if 0
{

		.name	= TVP7002_INST0,
		.board_info = {
			/* TODO Find the correct address
				of the TVP7002 connected */
			I2C_BOARD_INFO("tvp7002", 0x5d),
			.platform_data = &tvp7002_pdata,
		},
		.vip_port_cfg = {
			.ctrlChanSel = VPS_VIP_CTRL_CHAN_SEL_15_8,
			.ancChSel8b = VPS_VIP_ANC_CH_SEL_DONT_CARE,
			.pixClkEdgePol = VPS_VIP_PIX_CLK_EDGE_POL_RISING,
			.invertFidPol = 0,
			.embConfig = {
				.errCorrEnable = 1,
				.srcNumPos = VPS_VIP_SRC_NUM_POS_DONT_CARE,
				.isMaxChan3Bits = 0,
			},
			.disConfig = {
				.fidSkewPostCnt = 0,
				.fidSkewPreCnt = 0,
				.lineCaptureStyle =
					VPS_VIP_LINE_CAPTURE_STYLE_DONT_CARE,
				.fidDetectMode =
					VPS_VIP_FID_DETECT_MODE_DONT_CARE,
				.actvidPol = VPS_VIP_POLARITY_DONT_CARE,
				.vsyncPol =  VPS_VIP_POLARITY_DONT_CARE,
				.hsyncPol = VPS_VIP_POLARITY_DONT_CARE,
			}
		},
		.video_capture_mode =
		   VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_EMBEDDED_SYNC,
		.video_if_mode = VPS_CAPT_VIDEO_IF_MODE_16BIT,
		.input_data_format = FVID2_DF_YUV422P,
	},
	
	{
		.name	= TVP7002_INST1,
		.board_info = {
			I2C_BOARD_INFO("tvp7002", 0x5c),
			.platform_data = &tvp514x_pdata,
		},
		.vip_port_cfg = {
			.ctrlChanSel = VPS_VIP_CTRL_CHAN_SEL_15_8,
			.ancChSel8b = VPS_VIP_ANC_CH_SEL_DONT_CARE,
			.pixClkEdgePol = VPS_VIP_PIX_CLK_EDGE_POL_RISING,
			.invertFidPol = 0,
			.embConfig = {
				.errCorrEnable = 1,
				.srcNumPos = VPS_VIP_SRC_NUM_POS_DONT_CARE,
				.isMaxChan3Bits = 0,
			},
			.disConfig = {
				.fidSkewPostCnt = 0,
				.fidSkewPreCnt = 0,
				.lineCaptureStyle =
					VPS_VIP_LINE_CAPTURE_STYLE_DONT_CARE,
				.fidDetectMode =
					VPS_VIP_FID_DETECT_MODE_DONT_CARE,
				.actvidPol = VPS_VIP_POLARITY_DONT_CARE,
				.vsyncPol =  VPS_VIP_POLARITY_DONT_CARE,
				.hsyncPol = VPS_VIP_POLARITY_DONT_CARE,
			}
		},
		.video_capture_mode =
		   VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_EMBEDDED_SYNC,
		.video_if_mode = VPS_CAPT_VIDEO_IF_MODE_16BIT,
		.input_data_format = FVID2_DF_YUV422P,
	},

{
		.name	= "tvp5147",//TVP7002_INST1,
		.board_info = {
			I2C_BOARD_INFO("tvp5147", 0x5d),
			.platform_data = &tvp514x_pdata,
		},
		.vip_port_cfg = {
			.ctrlChanSel = VPS_VIP_CTRL_CHAN_SEL_15_8,
			.ancChSel8b = VPS_VIP_ANC_CH_SEL_DONT_CARE,
			.pixClkEdgePol = VPS_VIP_PIX_CLK_EDGE_POL_RISING,
			.invertFidPol = 1,//0,
			.embConfig = {
				.errCorrEnable = 1,
				.srcNumPos = VPS_VIP_SRC_NUM_POS_DONT_CARE,
				.isMaxChan3Bits = 0,
			},
			.disConfig = {
				.fidSkewPostCnt = 0,
				.fidSkewPreCnt = 0,
				.lineCaptureStyle =
					VPS_VIP_LINE_CAPTURE_STYLE_DONT_CARE,
				.fidDetectMode =
					VPS_VIP_FID_DETECT_MODE_DONT_CARE,
				.actvidPol = VPS_VIP_POLARITY_DONT_CARE,
				.vsyncPol =  VPS_VIP_POLARITY_DONT_CARE,
				.hsyncPol = VPS_VIP_POLARITY_DONT_CARE,
			}
		},
		.video_capture_mode =
		   VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_EMBEDDED_SYNC,
		.video_if_mode = VPS_CAPT_VIDEO_IF_MODE_8BIT,//VPS_CAPT_VIDEO_IF_MODE_16BIT,
		.input_data_format = FVID2_DF_YUV422I_UYVY,//FVID2_DF_YUV422P,
	},
#endif
{
		.name	= "tvp5147m1",//TVP7002_INST1,
		.board_info = {
			I2C_BOARD_INFO("tvp5147m1", 0x5c),
			.platform_data = &tvp514x_pdata,
		},
		.vip_port_cfg = {
			.ctrlChanSel = VPS_VIP_CTRL_CHAN_SEL_15_8,
			.ancChSel8b = VPS_VIP_ANC_CH_SEL_DONT_CARE,
			.pixClkEdgePol = VPS_VIP_PIX_CLK_EDGE_POL_RISING,
			.invertFidPol = 1,//0,
			.embConfig = {
				.errCorrEnable = 1,
				.srcNumPos = VPS_VIP_SRC_NUM_POS_DONT_CARE,
				.isMaxChan3Bits = 0,
			},
			.disConfig = {
				.fidSkewPostCnt = 0,
				.fidSkewPreCnt = 0,
				.lineCaptureStyle =
					VPS_VIP_LINE_CAPTURE_STYLE_DONT_CARE,
				.fidDetectMode =
					VPS_VIP_FID_DETECT_MODE_DONT_CARE,
				.actvidPol = VPS_VIP_POLARITY_DONT_CARE,
				.vsyncPol =  VPS_VIP_POLARITY_DONT_CARE,
				.hsyncPol = VPS_VIP_POLARITY_DONT_CARE,
			}
		},
		.video_capture_mode =
		   VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_EMBEDDED_SYNC,
		.video_if_mode = VPS_CAPT_VIDEO_IF_MODE_16BIT,//VPS_CAPT_VIDEO_IF_MODE_8BIT,
		.input_data_format = FVID2_DF_YUV422I_UYVY,//FVID2_DF_YUV422P,
	},
};

static const struct v4l2_dv_preset hdvpss_inst0_inp0_presets[] = {
#if 0	
{
		.preset = V4L2_DV_720P60,
	},
	{
		.preset = V4L2_DV_1080I60,
	},
	{
		.preset = V4L2_DV_1080P60,
	},
	{
		.preset = V4L2_DV_1080P30,
	},
#endif	
{
		.preset = V4L2_DV_576P50,
  	},
  	{
 		.preset = V4L2_DV_480P59_94,
  	},
};

static const struct v4l2_dv_preset hdvpss_inst2_inp0_presets[] = {
#if 0	
{
		.preset = V4L2_DV_720P60,
	},
	{
		.preset = V4L2_DV_1080I60,
	},
	{
		.preset = V4L2_DV_1080P60,
	},
	{
		.preset = V4L2_DV_1080P30,
	},
 #endif	
{
		.preset = V4L2_DV_576P50,
  	},
  	{
 		.preset = V4L2_DV_480P59_94,
  	},
};

static const struct ti81xxvin_input hdvpss_inst0_inputs[] = {
	{
		.input = {
			.index		= 0,
			.name		= "Composite",
			.type		= V4L2_INPUT_TYPE_CAMERA,
			.std		= V4L2_STD_ALL,//V4L2_STD_UNKNOWN,
			.capabilities	= V4L2_OUT_CAP_PRESETS,
		},
		.subdev_name	= "tv5147m1",//TVP7002_INST0,
		.dv_presets	= hdvpss_inst0_inp0_presets,
		.num_dv_presets	= ARRAY_SIZE(hdvpss_inst0_inp0_presets),
	},
};

static const struct ti81xxvin_input hdvpss_inst1_inputs[] = {
	{
		.input = {
			.index		= 0,
			.name		= "Composite",
			.type		= V4L2_INPUT_TYPE_CAMERA,
			.std		= V4L2_STD_ALL,//V4L2_STD_UNKNOWN,
			.capabilities	= V4L2_IN_CAP_STD//V4L2_OUT_CAP_PRESETS,
		},
		.subdev_name	= "tv5147m1",//TVP7002_INST1,
		.dv_presets	= hdvpss_inst2_inp0_presets,
		.num_dv_presets	= ARRAY_SIZE(hdvpss_inst2_inp0_presets),
	},
};

/* 16 bit decoders are present on the Port A of VIP0 and VIP1 instances. Which
represents the VIP0 and VIP2 instances in software. While Port B of VIP0 and
VIP1 are represented by VIP1 and VIP3 instances. On these two instances no
decoders are present.
*/
static struct ti81xxvin_config ti81xx_hsvpss_capture_cfg = {
	.subdev_info = hdvpss_capture_sdev_info,
	.subdev_count = ARRAY_SIZE(hdvpss_capture_sdev_info),
	.card_name = ti81xx_card_name,
	.inst_config[0] = {
		.inputs = hdvpss_inst0_inputs,
		.input_count = ARRAY_SIZE(hdvpss_inst0_inputs),
	},
	.inst_config[1] = {
		.inputs = hdvpss_inst0_inputs,
		.input_count = 0,
	},
	.inst_config[2] = {
		.inputs = hdvpss_inst1_inputs,
		.input_count = ARRAY_SIZE(hdvpss_inst1_inputs),
	},
	.inst_config[3] = {
		.inputs = hdvpss_inst1_inputs,
		.input_count = 0,
	},

};

static struct resource ti81xx_hdvpss_capture_resource[] = {
	[0] = {
		.start = HDVPSS_CAPTURE_INST0_BASE,
		.end   = (HDVPSS_CAPTURE_INST0_BASE +
				HDVPSS_CAPTURE_INST0_SIZE - 1),
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = HDVPSS_CAPTURE_INST2_BASE,
		.end   = (HDVPSS_CAPTURE_INST2_BASE +
				HDVPSS_CAPTURE_INST2_SIZE - 1),
		.flags = IORESOURCE_MEM,
	},
};

static struct platform_device hdvpss_capture_dev = {
	.name		= "ti81xxvin",
	.id		= -1,
	.dev		= {
			.dma_mask		= &ti81xx_dma_mask,
			.coherent_dma_mask	= ~(u32)0,
	},
	.num_resources = 2,
	.resource = ti81xx_hdvpss_capture_resource,
};

static int __init ti81xx_vin_init(void)
{
	int r;
printk("%s, %s\n",__FILE__,__FUNCTION__);
	hdvpss_capture_dev.dev.platform_data = &ti81xx_hsvpss_capture_cfg;
	if (cpu_is_ti814x()) {
		hdvpss_capture_sdev_info[0].ti81xxvin_select_decoder =NULL;
			//vps_ti814x_select_video_decoder;
		hdvpss_capture_sdev_info[0].ti81xxvin_set_mode =NULL;
			//vps_ti814x_set_tvp7002_filter;
		hdvpss_capture_sdev_info[0].decoder_id = 0;
		hdvpss_capture_sdev_info[1].ti81xxvin_select_decoder =
			NULL;
		hdvpss_capture_sdev_info[1].ti81xxvin_set_mode =
			NULL;
		hdvpss_capture_sdev_info[1].decoder_id = 0;
	} else {
		hdvpss_capture_sdev_info[0].ti81xxvin_select_decoder =
			//vps_ti816x_select_video_decoder;
NULL;
		hdvpss_capture_sdev_info[0].ti81xxvin_set_mode =
			//vps_ti816x_set_tvp7002_filter;
NULL;
		hdvpss_capture_sdev_info[0].decoder_id = 0;
		hdvpss_capture_sdev_info[1].ti81xxvin_select_decoder =
			NULL;
		hdvpss_capture_sdev_info[1].ti81xxvin_set_mode =
			NULL;
		hdvpss_capture_sdev_info[1].decoder_id = 0;
	}
	r = platform_device_register(&hdvpss_capture_dev);
	if (r)
		printk(KERN_ERR "unable to register ti81xx_vin device\n");
	else
		printk(KERN_INFO "registered ti81xx_vin device\n");
	return r;

}
#else
static int __init ti81xx_vin_init(void)
{
	return 0;
}

#endif

#if defined(CONFIG_FB_TI81XX_MODULE) || defined(CONFIG_FB_TI81XX)
static struct ti81xxfb_platform_data ti81xxfb_config;

static struct platform_device ti81xx_fb_device = {
	.name		= "ti81xxfb",
	.id		= -1,
	.dev = {
		.dma_mask		= &ti81xx_dma_mask,
		.coherent_dma_mask	= ~(u32)0,
		.platform_data		= &ti81xxfb_config,
	},
	.num_resources = 0,
};


void ti81xxfb_set_platform_data(struct ti81xxfb_platform_data *data)
{
	ti81xxfb_config = *data;
}

static int __init ti81xx_fb_init(void)
{
	int r;
	r = platform_device_register(&ti81xx_fb_device);
	if (r)
		printk(KERN_ERR "unable to register ti81xx_fb device\n");
	else
		printk(KERN_INFO "registered ti81xx_fb device\n");
	return r;

}
#else
static int __init ti81xx_fb_init(void)
{
	return 0;
}
void ti81xxfb_set_platform_data(struct ti81xxfb_platform_data *data)
{
}
#endif

#if defined(CONFIG_VIDEO_TI81XX_VIDOUT_MODULE) || \
		defined(CONFIG_VIDEO_TI81XX_VIDOUT)
static struct resource ti81xx_vidout_resource[VPS_DISPLAY_INST_MAX] = {
};

static struct platform_device ti81xx_vidout_device = {
	.name		= "t81xx_vidout",
	.num_resources  = ARRAY_SIZE(ti81xx_vidout_resource),
	.resource       = &ti81xx_vidout_resource[0],
	.id             = -1,
};

static int __init ti81xx_init_vout(void)
{
	int r;

	r = platform_device_register(&ti81xx_vidout_device);
	if (r)
		printk(KERN_ERR "Unable to register ti81xx_vidout device\n");
	else
		printk(KERN_INFO "registered ti81xx_vidout device\n");
	return r;
}
#else
static int __init ti81xx_init_vout(void)
{
	return 0;
}
#endif


static int __init ti81xx_init_vpss(void)
{
	int retval = 0;
printk("%s, %s\n",__FILE__,__FUNCTION__);
	/*if vpss failed to register, none of the below could works*/
	if (ti81xx_vpss_init())
		return -1;
	retval = ti81xx_init_vout();
	retval += ti81xx_hdmi_init();
	retval += ti81xx_fb_init();
	retval += ti81xx_vin_init();
	return retval;
}

arch_initcall(ti81xx_init_vpss);

#endif

/* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics
 * Digitizer with Horizontal PLL registers
 *
 * Copyright (C) 2009 Texas Instruments Inc
 * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>
 *
 * This code is partially based upon the TVP5150 driver
 * written by Mauro Carvalho Chehab (mchehab@infradead.org),
 * the TVP514x driver written by Vaibhav Hiremath <hvaibhav@ti.com>
 * and the TVP5147 driver in the TI LSP 2.10.00.14. Revisions by
 * Muralidharan Karicheri and Snehaprabha Narnakaje (TI).
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/videodev2.h>
#include <media/tvp5147.h>
#include <media/v4l2-device.h>
#include <media/v4l2-chip-ident.h>
#include <media/v4l2-common.h>
#include "tvp5147_reg.h"

MODULE_DESCRIPTION("TI TVP5147 Video and Graphics Digitizer driver");
MODULE_AUTHOR("Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>");
MODULE_LICENSE("GPL");

/* Module Name */
#define TVP5147_MODULE_NAME	"tvp5147"

/* I2C retry attempts */
#define I2C_RETRY_COUNT		(4)

/* End of registers */
#define TVP5147_EOR		0xf8

/* Read write definition for registers */
#define TVP5147_READ		0
#define TVP5147_WRITE		1
#define TVP5147_RESERVED	2

/* Interlaced vs progressive mask and shift */
#define TVP5147_IP_SHIFT	5
#define TVP5147_INPR_MASK	(0x01 << TVP5147_IP_SHIFT)

/* Shift for CPL and LPF registers */
#define TVP5147_CL_SHIFT	8
#define TVP5147_CL_MASK		0x0f

/* Debug functions */
static int debug;
module_param(debug, bool, 0644);
MODULE_PARM_DESC(debug, "Debug level (0-1)");

/* Structure for register values */
struct i2c_reg_value {
	u8 reg;
	u8 value;
	u8 type;
};


/* Preset definition for handling device operation */
struct tvp5147_preset_definition {                                              // Ajout
	char name[50];
	u32 preset;
	const struct i2c_reg_value *p_settings;
	enum v4l2_colorspace color_space;
	enum v4l2_field scanmode;
	u16 progressive;
	u16 lines_per_frame;
	u16 cpl_min;
	u16 cpl_max;
};

/*
 * Register default values (according to tvp5147 datasheet)
 * In the case of read-only registers, the value (0xff) is
 * never written. R/W functionality is controlled by the
 * writable bit in the register struct definition.
 */
static const struct i2c_reg_value tvp5147_init_default[] = {
	{ 0X00, 0x00, TVP5147_WRITE },
	{ 0X01, 0x0F, TVP5147_WRITE },
	{ 0X02, 0x00, TVP5147_WRITE },
	{ 0X03, 0x00, TVP5147_WRITE },
	{ 0X04, 0x23, TVP5147_WRITE },
	{ 0X05, 0x10, TVP5147_WRITE },
	{ 0X06, 0x00, TVP5147_WRITE },
	{ 0X07, 0x00, TVP5147_WRITE },
	{ 0X08, 0x00, TVP5147_WRITE },
	{ 0X09, 0x02, TVP5147_WRITE },
	{ 0X0A, 0x80, TVP5147_WRITE },
	{ 0X0B, 0x80, TVP5147_WRITE },
	{ 0X0C, 0x00, TVP5147_WRITE },
	{ 0X0D, 0x00, TVP5147_WRITE },
	{ 0X0E, 0x0E, TVP5147_WRITE },
//RESERVED 0X0F - 0X15
	{ 0X17, 0x55, TVP5147_WRITE },
	{ 0X16, 0x00, TVP5147_WRITE },
	{ 0X19, 0x25, TVP5147_WRITE },
	{ 0X18, 0x03, TVP5147_WRITE },	
	{ 0X1A, 0x00, TVP5147_WRITE },
	{ 0X1B, 0x00, TVP5147_WRITE },
	{ 0X1C, 0x00, TVP5147_WRITE },
	{ 0X1D, 0x40, TVP5147_WRITE },
	{ 0X1E, 0x00, TVP5147_WRITE },
	{ 0X1F, 0x04, TVP5147_WRITE },
	{ 0X20, 0x00, TVP5147_WRITE },
	{ 0X21, 0x07, TVP5147_WRITE },
	{ 0X22, 0x00, TVP5147_WRITE },
	{ 0X23, 0x01, TVP5147_WRITE },
	{ 0X24, 0x00, TVP5147_WRITE },
	{ 0X25, 0x15, TVP5147_WRITE },
//RESERVED 0X26-0X2A
	{ 0X2B, 0x00, TVP5147_WRITE },
//RESERVED 0X2C
	{ 0X2D, 0x00, TVP5147_WRITE },
	{ 0X2E, 0x00, TVP5147_WRITE },
//RESERVED 0X2F-0X30
	{ 0X31, 0x05, TVP5147_WRITE },
	{ 0X32, 0x00, TVP5147_WRITE },
	{ 0X33, 0x40, TVP5147_WRITE },
	{ 0X34, 0x00, TVP5147_WRITE },
	{ 0X35, 0xFF, TVP5147_WRITE },
	{ 0X36, 0xFF, TVP5147_WRITE },
	{ 0X37, 0xFF, TVP5147_WRITE },
	{ 0X38, 0xFF, TVP5147_WRITE },
	{ 0X39, 0x00, TVP5147_WRITE },

	{ 0X46 , 0x20, TVP5147_WRITE },
	{ 0X47 , 0x20, TVP5147_WRITE },
	{ 0X48 , 0x20, TVP5147_WRITE },
	{ 0X49 , 0x20, TVP5147_WRITE },
	{ 0X4A , 0x90, TVP5147_WRITE },
	{ 0X4B , 0x00, TVP5147_WRITE },
	{ 0X4C , 0x90, TVP5147_WRITE },
	{ 0X4D , 0x00, TVP5147_WRITE },
	{ 0X4E , 0x90, TVP5147_WRITE },
	{ 0X4F , 0x00, TVP5147_WRITE },
	{ 0X50 , 0x90, TVP5147_WRITE },
	{ 0X51 , 0x00, TVP5147_WRITE },

	{ 0X57 , 0x00, TVP5147_WRITE },

	{ 0X74 , 0x00, TVP5147_WRITE },
	{ 0X75 , 0x12, TVP5147_WRITE },
	{ 0X76 , 0x8A, TVP5147_WRITE },
	{ 0X77 , 0x64, TVP5147_WRITE },
	{ 0X78 , 0x05, TVP5147_WRITE },
	{ 0X79 , 0x1E, TVP5147_WRITE },

	{ 0X7F , 0x00, TVP5147_WRITE },
	{ 0X80 , 0x51, TVP5147_READ },
	{ 0X81 , 0x47, TVP5147_READ},

	{ 0XB1 , 0x00, TVP5147_WRITE },
	{ 0XB2 , 0x00, TVP5147_WRITE },
	{ 0XB3 , 0x00, TVP5147_WRITE },
	{ 0XB4 , 0x00, TVP5147_WRITE },
	{ 0XB5 , 0x00, TVP5147_WRITE },
	{ 0XB6 , 0x00, TVP5147_WRITE },
	{ 0XB7 , 0x00, TVP5147_WRITE },
	{ 0XB8 , 0x00, TVP5147_WRITE },
	{ 0XB9 , 0x00, TVP5147_WRITE },
	{ 0XBA , 0x00, TVP5147_WRITE },
	{ 0XBB , 0x00, TVP5147_WRITE },

	{ 0XBD , 0x80, TVP5147_WRITE },

	{ 0XBF , 0x00, TVP5147_WRITE },
	{ 0XC0 , 0x00, TVP5147_WRITE },
	{ 0XC1 , 0x00, TVP5147_WRITE },
	{ 0XC2 , 0x00, TVP5147_WRITE },
	{ 0XC3 , 0x1E, TVP5147_WRITE },

	{ 0XD6 , 0x06, TVP5147_WRITE },
	{ 0XD7 , 0x1B, TVP5147_WRITE },
	{ 0XD8 , 0xFF, TVP5147_WRITE },
	{ 0XD9 , 0x00, TVP5147_WRITE },
	{ 0XDA , 0xFF, TVP5147_WRITE },

	{ 0XE0 , 0x00, TVP5147_WRITE },
	{ 0XE1 , 0x00, TVP5147_WRITE },

	{ 0XE8 , 0x00, TVP5147_WRITE },
	{ 0XE9 , 0x00, TVP5147_WRITE },
	{ 0XEA , 0x00, TVP5147_WRITE },

	{ 0XF4 , 0x00, TVP5147_WRITE },
	{ 0XF5 , 0x00, TVP5147_WRITE },
	{ 0XF6 , 0x00, TVP5147_WRITE },
	{ 0XF7 , 0x00, TVP5147_WRITE },

/* This signals end of register values */
	{ TVP5147_EOR, 0xf8, TVP5147_RESERVED }
};
#if 0
/* Register parameters for 480P */
static const struct i2c_reg_value tvp5147_parms_480P[] = {
	{ TVP5147_HPLL_FDBK_DIV_MSBS, 0x35, TVP5147_WRITE },
	{ TVP5147_HPLL_FDBK_DIV_LSBS, 0xa0, TVP5147_WRITE },
	{ TVP5147_HPLL_CRTL, 0x02, TVP5147_WRITE },
	{ TVP5147_HPLL_PHASE_SEL, 0x14, TVP5147_WRITE },
	{ TVP5147_AVID_START_PIXEL_LSBS, 0x91, TVP5147_WRITE },
	{ TVP5147_AVID_START_PIXEL_MSBS, 0x00, TVP5147_WRITE },
	{ TVP5147_AVID_STOP_PIXEL_LSBS, 0x0B, TVP5147_WRITE },
	{ TVP5147_AVID_STOP_PIXEL_MSBS, 0x00, TVP5147_WRITE },
	{ TVP5147_VBLK_F_0_START_L_OFF, 0x03, TVP5147_WRITE },
	{ TVP5147_VBLK_F_1_START_L_OFF, 0x01, TVP5147_WRITE },
	{ TVP5147_VBLK_F_0_DURATION, 0x13, TVP5147_WRITE },
	{ TVP5147_VBLK_F_1_DURATION, 0x13, TVP5147_WRITE },
	{ TVP5147_ALC_PLACEMENT, 0x18, TVP5147_WRITE },
	{ TVP5147_CLAMP_START, 0x06, TVP5147_WRITE },
	{ TVP5147_CLAMP_W, 0x10, TVP5147_WRITE },
	{ TVP5147_HPLL_PRE_COAST, 0x03, TVP5147_WRITE },
	{ TVP5147_HPLL_POST_COAST, 0x03, TVP5147_WRITE },
	{ TVP5147_EOR, 0xff, TVP5147_RESERVED }
};

/* Register parameters for 576P */
static const struct i2c_reg_value tvp5147_parms_576P[] = {
	{ TVP5147_HPLL_FDBK_DIV_MSBS, 0x36, TVP5147_WRITE },
	{ TVP5147_HPLL_FDBK_DIV_LSBS, 0x00, TVP5147_WRITE },
	{ TVP5147_HPLL_CRTL, 0x18, TVP5147_WRITE },
	{ TVP5147_HPLL_PHASE_SEL, 0x14, TVP5147_WRITE },
	{ TVP5147_AVID_START_PIXEL_LSBS, 0x9B, TVP5147_WRITE },
	{ TVP5147_AVID_START_PIXEL_MSBS, 0x00, TVP5147_WRITE },
	{ TVP5147_AVID_STOP_PIXEL_LSBS, 0x0F, TVP5147_WRITE },
	{ TVP5147_AVID_STOP_PIXEL_MSBS, 0x00, TVP5147_WRITE },
	{ TVP5147_VBLK_F_0_START_L_OFF, 0x00, TVP5147_WRITE },
	{ TVP5147_VBLK_F_1_START_L_OFF, 0x00, TVP5147_WRITE },
	{ TVP5147_VBLK_F_0_DURATION, 0x2D, TVP5147_WRITE },
	{ TVP5147_VBLK_F_1_DURATION, 0x00, TVP5147_WRITE },
	{ TVP5147_ALC_PLACEMENT, 0x18, TVP5147_WRITE },
	{ TVP5147_CLAMP_START, 0x06, TVP5147_WRITE },
	{ TVP5147_CLAMP_W, 0x10, TVP5147_WRITE },
	{ TVP5147_HPLL_PRE_COAST, 0x03, TVP5147_WRITE },
	{ TVP5147_HPLL_POST_COAST, 0x03, TVP5147_WRITE },
	{ TVP5147_EOR, 0xff, TVP5147_RESERVED }
};

/* Register parameters for 1080I60 */
static const struct i2c_reg_value tvp5147_parms_1080I60[] = {
	{ TVP5147_HPLL_FDBK_DIV_MSBS, 0x89, TVP5147_WRITE },
	{ TVP5147_HPLL_FDBK_DIV_LSBS, 0x80, TVP5147_WRITE },
	{ TVP5147_HPLL_CRTL, 0x98, TVP5147_WRITE },
	{ TVP5147_HPLL_PHASE_SEL, 0x14, TVP5147_WRITE },
	{ TVP5147_AVID_START_PIXEL_LSBS, 0x06, TVP5147_WRITE },
	{ TVP5147_AVID_START_PIXEL_MSBS, 0x01, TVP5147_WRITE },
	{ TVP5147_AVID_STOP_PIXEL_LSBS, 0x8a, TVP5147_WRITE },
	{ TVP5147_AVID_STOP_PIXEL_MSBS, 0x08, TVP5147_WRITE },
	{ TVP5147_VBLK_F_0_START_L_OFF, 0x02, TVP5147_WRITE },
	{ TVP5147_VBLK_F_1_START_L_OFF, 0x02, TVP5147_WRITE },
	{ TVP5147_VBLK_F_0_DURATION, 0x16, TVP5147_WRITE },
	{ TVP5147_VBLK_F_1_DURATION, 0x17, TVP5147_WRITE },
	{ TVP5147_ALC_PLACEMENT, 0x5a, TVP5147_WRITE },
	{ TVP5147_CLAMP_START, 0x32, TVP5147_WRITE },
	{ TVP5147_CLAMP_W, 0x20, TVP5147_WRITE },
	{ TVP5147_HPLL_PRE_COAST, 0x01, TVP5147_WRITE },
	{ TVP5147_HPLL_POST_COAST, 0x00, TVP5147_WRITE },
	{ TVP5147_EOR, 0xff, TVP5147_RESERVED }
};

/* Register parameters for 1080P60 */
static const struct i2c_reg_value tvp5147_parms_1080P60[] = {
	{ TVP5147_HPLL_FDBK_DIV_MSBS, 0x89, TVP5147_WRITE },
	{ TVP5147_HPLL_FDBK_DIV_LSBS, 0x80, TVP5147_WRITE },
	{ TVP5147_HPLL_CRTL, 0xE0, TVP5147_WRITE },
	{ TVP5147_HPLL_PHASE_SEL, 0xA0, TVP5147_WRITE },
	{ TVP5147_AVID_START_PIXEL_LSBS, 0x00, TVP5147_WRITE },
	{ TVP5147_AVID_START_PIXEL_MSBS, 0x01, TVP5147_WRITE },
	{ TVP5147_AVID_STOP_PIXEL_LSBS, 0x84, TVP5147_WRITE },
	{ TVP5147_AVID_STOP_PIXEL_MSBS, 0x08, TVP5147_WRITE },
	{ TVP5147_VBLK_F_0_START_L_OFF, 0x05, TVP5147_WRITE },
	{ TVP5147_VBLK_F_1_START_L_OFF, 0x00, TVP5147_WRITE },
	{ TVP5147_VBLK_F_0_DURATION, 0x2d, TVP5147_WRITE },
	{ TVP5147_VBLK_F_1_DURATION, 0x0, TVP5147_WRITE },
	{ TVP5147_ALC_PLACEMENT, 0x5a, TVP5147_WRITE },
	{ TVP5147_CLAMP_START, 0x32, TVP5147_WRITE },
	{ TVP5147_CLAMP_W, 0x20, TVP5147_WRITE },
	{ TVP5147_HPLL_PRE_COAST, 0x01, TVP5147_WRITE },
	{ TVP5147_HPLL_POST_COAST, 0x00, TVP5147_WRITE },
	{ TVP5147_EOR, 0xff, TVP5147_RESERVED }
};

/* Register parameters for 1080I50 */
static const struct i2c_reg_value tvp5147_parms_1080I50[] = {
	{ TVP5147_HPLL_FDBK_DIV_MSBS, 0xa5, TVP5147_WRITE },
	{ TVP5147_HPLL_FDBK_DIV_LSBS, 0x00, TVP5147_WRITE },
	{ TVP5147_HPLL_CRTL, 0x98, TVP5147_WRITE },
	{ TVP5147_HPLL_PHASE_SEL, 0x14, TVP5147_WRITE },
	{ TVP5147_AVID_START_PIXEL_LSBS, 0x06, TVP5147_WRITE },
	{ TVP5147_AVID_START_PIXEL_MSBS, 0x01, TVP5147_WRITE },
	{ TVP5147_AVID_STOP_PIXEL_LSBS, 0x8a, TVP5147_WRITE },
	{ TVP5147_AVID_STOP_PIXEL_MSBS, 0x08, TVP5147_WRITE },
	{ TVP5147_VBLK_F_0_START_L_OFF, 0x02, TVP5147_WRITE },
	{ TVP5147_VBLK_F_1_START_L_OFF, 0x02, TVP5147_WRITE },
	{ TVP5147_VBLK_F_0_DURATION, 0x16, TVP5147_WRITE },
	{ TVP5147_VBLK_F_1_DURATION, 0x17, TVP5147_WRITE },
	{ TVP5147_ALC_PLACEMENT, 0x5a, TVP5147_WRITE },
	{ TVP5147_CLAMP_START, 0x32, TVP5147_WRITE },
	{ TVP5147_CLAMP_W, 0x20, TVP5147_WRITE },
	{ TVP5147_HPLL_PRE_COAST, 0x01, TVP5147_WRITE },
	{ TVP5147_HPLL_POST_COAST, 0x00, TVP5147_WRITE },
	{ TVP5147_EOR, 0xff, TVP5147_RESERVED }
};

/* Register parameters for 720P60 */
static const struct i2c_reg_value tvp5147_parms_720P60[] = {
	{ TVP5147_HPLL_FDBK_DIV_MSBS, 0x67, TVP5147_WRITE },
	{ TVP5147_HPLL_FDBK_DIV_LSBS, 0x20, TVP5147_WRITE },
	{ TVP5147_HPLL_CRTL, 0xa0, TVP5147_WRITE },
	{ TVP5147_HPLL_PHASE_SEL, 0x16, TVP5147_WRITE },
	{ TVP5147_AVID_START_PIXEL_LSBS, 0x47, TVP5147_WRITE },
	{ TVP5147_AVID_START_PIXEL_MSBS, 0x01, TVP5147_WRITE },
	{ TVP5147_AVID_STOP_PIXEL_LSBS, 0x4B, TVP5147_WRITE },
	{ TVP5147_AVID_STOP_PIXEL_MSBS, 0x06, TVP5147_WRITE },
	{ TVP5147_VBLK_F_0_START_L_OFF, 0x05, TVP5147_WRITE },
	{ TVP5147_VBLK_F_1_START_L_OFF, 0x00, TVP5147_WRITE },
	{ TVP5147_VBLK_F_0_DURATION, 0x1E, TVP5147_WRITE },
	{ TVP5147_VBLK_F_1_DURATION, 0x00, TVP5147_WRITE },
	{ TVP5147_ALC_PLACEMENT, 0x5a, TVP5147_WRITE },
	{ TVP5147_CLAMP_START, 0x32, TVP5147_WRITE },
	{ TVP5147_CLAMP_W, 0x20, TVP5147_WRITE },
	{ TVP5147_HPLL_PRE_COAST, 0x00, TVP5147_WRITE },
	{ TVP5147_HPLL_POST_COAST, 0x00, TVP5147_WRITE },
	{ TVP5147_EOR, 0xff, TVP5147_RESERVED }
};

/* Register parameters for 720P50 */
static const struct i2c_reg_value tvp5147_parms_720P50[] = {
	{ TVP5147_HPLL_FDBK_DIV_MSBS, 0x7b, TVP5147_WRITE },
	{ TVP5147_HPLL_FDBK_DIV_LSBS, 0xc0, TVP5147_WRITE },
	{ TVP5147_HPLL_CRTL, 0x98, TVP5147_WRITE },
	{ TVP5147_HPLL_PHASE_SEL, 0x16, TVP5147_WRITE },
	{ TVP5147_AVID_START_PIXEL_LSBS, 0x47, TVP5147_WRITE },
	{ TVP5147_AVID_START_PIXEL_MSBS, 0x01, TVP5147_WRITE },
	{ TVP5147_AVID_STOP_PIXEL_LSBS, 0x4B, TVP5147_WRITE },
	{ TVP5147_AVID_STOP_PIXEL_MSBS, 0x06, TVP5147_WRITE },
	{ TVP5147_VBLK_F_0_START_L_OFF, 0x05, TVP5147_WRITE },
	{ TVP5147_VBLK_F_1_START_L_OFF, 0x00, TVP5147_WRITE },
	{ TVP5147_VBLK_F_0_DURATION, 0x2D, TVP5147_WRITE },
	{ TVP5147_VBLK_F_1_DURATION, 0x00, TVP5147_WRITE },
	{ TVP5147_ALC_PLACEMENT, 0x5a, TVP5147_WRITE },
	{ TVP5147_CLAMP_START, 0x32, TVP5147_WRITE },
	{ TVP5147_CLAMP_W, 0x20, TVP5147_WRITE },
	{ TVP5147_HPLL_PRE_COAST, 0x01, TVP5147_WRITE },
	{ TVP5147_HPLL_POST_COAST, 0x00, TVP5147_WRITE },
	{ TVP5147_EOR, 0xff, TVP5147_RESERVED }
};
#endif
/* Preset definition for handling device operation */
struct tvp5147_preset_definition {
	u32 preset;
	const struct i2c_reg_value *p_settings;
	enum v4l2_colorspace color_space;
	enum v4l2_field scanmode;
	u16 progressive;
	u16 lines_per_frame;
	u16 cpl_min;
	u16 cpl_max;
};

/* Struct list for digital video presets */
static const struct tvp5147_preset_definition tvp5147_presets[] = {/*TODO*/
	{
		V4L2_DV_720P60,
		tvp5147_parms_720P60,
		V4L2_COLORSPACE_REC709,
		V4L2_FIELD_NONE,
		1,
		0x2EE,
		135,
		153
	},
	{
		V4L2_DV_1080I60,
		tvp5147_parms_1080I60,
		V4L2_COLORSPACE_REC709,
		V4L2_FIELD_INTERLACED,
		0,
		0x465,
		181,
		205
	},
	{
		V4L2_DV_1080I50,
		tvp5147_parms_1080I50,
		V4L2_COLORSPACE_REC709,
		V4L2_FIELD_INTERLACED,
		0,
		0x465,
		217,
		245
	},
	{
		V4L2_DV_720P50,
		tvp5147_parms_720P50,
		V4L2_COLORSPACE_REC709,
		V4L2_FIELD_NONE,
		1,
		0x2EE,
		163,
		183
	},
	{
		V4L2_DV_1080P60,
		tvp5147_parms_1080P60,
		V4L2_COLORSPACE_REC709,
		V4L2_FIELD_NONE,
		1,
		0x465,
		90,
		102
	},
	{
		V4L2_DV_480P59_94,
		tvp5147_parms_480P,
		V4L2_COLORSPACE_SMPTE170M,
		V4L2_FIELD_NONE,
		1,
		0x20D,
		0xffff,
		0xffff
	},
	{
		V4L2_DV_576P50,
		tvp5147_parms_576P,
		V4L2_COLORSPACE_SMPTE170M,
		V4L2_FIELD_NONE,
		1,
		0x271,
		0xffff,
		0xffff
	}
};

#define NUM_PRESETS	ARRAY_SIZE(tvp5147_presets)

/* Device definition */
struct tvp5147 {
	struct v4l2_subdev sd;
	const struct tvp5147_config *pdata;

	int ver;
	int streaming;

	const struct tvp5147_preset_definition *current_preset;
	u8 gain;
};

/*
 * to_tvp5147 - Obtain device handler TVP5147
 * @sd: ptr to v4l2_subdev struct
 *
 * Returns device handler tvp5147.
 */
static inline struct tvp5147 *to_tvp5147(struct v4l2_subdev *sd)
{
	return container_of(sd, struct tvp5147, sd);
}

/*
 * tvp5147_read - Read a value from a register in an TVP5147
 * @sd: ptr to v4l2_subdev struct
 * @addr: TVP5147 register address
 * @dst: pointer to 8-bit destination
 *
 * Returns value read if successful, or non-zero (-1) otherwise.
 */
static int tvp5147_read(struct v4l2_subdev *sd, u8 addr, u8 *dst)
{
	struct i2c_client *c = v4l2_get_subdevdata(sd);
	int retry;
	int error;

	for (retry = 0; retry < I2C_RETRY_COUNT; retry++) {
		error = i2c_smbus_read_byte_data(c, addr);

		if (error >= 0) {
			*dst = (u8)error;
			return 0;
		}

		msleep_interruptible(10);
	}
	v4l2_err(sd, "TVP5147 read error %d\n", error);
	return error;
}

/*
 * tvp5147_read_err() - Read a register value with error code
 * @sd: pointer to standard V4L2 sub-device structure
 * @reg: destination register
 * @val: value to be read
 * @err: pointer to error value
 *
 * Read a value in a register and save error value in pointer.
 * Also update the register table if successful
 */
static inline void tvp5147_read_err(struct v4l2_subdev *sd, u8 reg,
							u8 *dst, int *err)
{
	if (!*err)
		*err = tvp5147_read(sd, reg, dst);
}

/*
 * tvp5147_write() - Write a value to a register in TVP5147
 * @sd: ptr to v4l2_subdev struct
 * @addr: TVP5147 register address
 * @value: value to be written to the register
 *
 * Write a value to a register in an TVP5147 decoder device.
 * Returns zero if successful, or non-zero otherwise.
 */
static int tvp5147_write(struct v4l2_subdev *sd, u8 addr, u8 value)
{
	struct i2c_client *c;
	int retry;
	int error;

	c = v4l2_get_subdevdata(sd);

	for (retry = 0; retry < I2C_RETRY_COUNT; retry++) {
		error = i2c_smbus_write_byte_data(c, addr, value);

		if (error >= 0)
			return 0;

		v4l2_warn(sd, "Write: retry !!! %d\n", retry);
		msleep_interruptible(10);
	}
	v4l2_err(sd, "TVP5147 write error %d\n", error);
	return error;
}

/*
 * tvp5147_write_err() - Write a register value with error code
 * @sd: pointer to standard V4L2 sub-device structure
 * @reg: destination register
 * @val: value to be written
 * @err: pointer to error value
 *
 * Write a value in a register and save error value in pointer.
 * Also update the register table if successful
 */
static inline void tvp5147_write_err(struct v4l2_subdev *sd, u8 reg,
							u8 val, int *err)
{
	if (!*err)
		*err = tvp5147_write(sd, reg, val);
}

/*
 * tvp5147_g_chip_ident() - Get chip identification number
 * @sd: ptr to v4l2_subdev struct
 * @chip: ptr to v4l2_dbg_chip_ident struct
 *
 * Obtains the chip's identification number.
 * Returns zero or -EINVAL if read operation fails.
 */
#if 0
static int tvp5147_g_chip_ident(struct v4l2_subdev *sd,
					struct v4l2_dbg_chip_ident *chip)
{
	u8 rev;
	int error;
	struct i2c_client *client = v4l2_get_subdevdata(sd);

	error = tvp5147_read(sd, TVP5147_CHIP_REV, &rev);

	if (error < 0)
		return error;

	return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_TVP5147, rev);
}
#else
/* --------------------------------------------------------------------------
 * V4L2 subdev core operations
 */
static int tvp5147_g_chip_ident(struct v4l2_subdev *subdev,
				struct v4l2_dbg_chip_ident *chip)
{
	struct i2c_client *client = v4l2_get_subdevdata(subdev);

	return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_TVP5147, 0);
}
#endif
/*
 * tvp5147_write_inittab() - Write initialization values
 * @sd: ptr to v4l2_subdev struct
 * @regs: ptr to i2c_reg_value struct
 *
 * Write initialization values.
 * Returns zero or -EINVAL if read operation fails.
 */
static int tvp5147_write_inittab(struct v4l2_subdev *sd,
					const struct i2c_reg_value *regs)
{
	int error = 0;

	/* Initialize the first (defined) registers */
	while (TVP5147_EOR != regs->reg) {
		if (TVP5147_WRITE == regs->type)
			tvp5147_write_err(sd, regs->reg, regs->value, &error);
		regs++;
	}

	return error;
}

/*
 * tvp5147_s_dv_preset() - Set digital video preset
 * @sd: ptr to v4l2_subdev struct
 * @dv_preset: ptr to v4l2_dv_preset struct
 *
 * Set the digital video preset for a TVP5147 decoder device.
 * Returns zero when successful or -EINVAL if register access fails.
 */
static int tvp5147_s_dv_preset(struct v4l2_subdev *sd,
					struct v4l2_dv_preset *dv_preset)
{
	struct tvp5147 *device = to_tvp5147(sd);
	u32 preset;
	int i;

	for (i = 0; i < NUM_PRESETS; i++) {
		preset = tvp5147_presets[i].preset;
		v4l2_info(sd, "-preset[%d] ------------------------------\n", i);
		v4l2_info(sd, "preset         = %s\n", 	tvp5158_presets[i].name);
		v4l2_info(sd, "reg=0x%X val=0x%X\n", 	tvp5158_presets[i].p_settings->reg, tvp5158_presets[i].p_settings->value);
		v4l2_info(sd, "color_space    = %d\n", 	tvp5158_presets[i].color_space);
		v4l2_info(sd, "scanmode       = %d\n", 	tvp5158_presets[i].scanmode);
		v4l2_info(sd, "progressive    = %d\n", 	tvp5158_presets[i].progressive);
		v4l2_info(sd, "lines_per_frame= %d\n", 	tvp5158_presets[i].lines_per_frame);
		v4l2_info(sd, "cpl_min        = %d\n", 	tvp5158_presets[i].cpl_min);
		v4l2_info(sd, "cpl_max        = %d\n", 	tvp5158_presets[i].cpl_max);
		if (preset == dv_preset->preset) {
			device->current_preset = &tvp5147_presets[i];
			return tvp5147_write_inittab(sd, tvp5147_presets[i].p_settings);
		}
	}
/*encore boucle for ??????????*/
	return -EINVAL;
}

/*
 * tvp5147_g_ctrl() - Get a control
 * @sd: ptr to v4l2_subdev struct
 * @ctrl: ptr to v4l2_control struct
 *
 * Get a control for a TVP5147 decoder device.
 * Returns zero when successful or -EINVAL if register access fails.
 */
static int tvp5147_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
{
	struct tvp5147 *device = to_tvp5147(sd);

	switch (ctrl->id) {
	case V4L2_CID_GAIN:
		ctrl->value = device->gain;
		return 0;
	default:
		return -EINVAL;
	}
}

/*
 * tvp5147_s_ctrl() - Set a control
 * @sd: ptr to v4l2_subdev struct
 * @ctrl: ptr to v4l2_control struct
 *
 * Set a control in TVP5147 decoder device.
 * Returns zero when successful or -EINVAL if register access fails.
 */
static int tvp5147_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
{
	struct tvp5147 *device = to_tvp5147(sd);
	int error = 0;

	switch (ctrl->id) {
	case V4L2_CID_GAIN:
		tvp5147_write_err(sd, TVP5147_R_FINE_GAIN,
						ctrl->value & 0xff, &error);
		tvp5147_write_err(sd, TVP5147_G_FINE_GAIN,
						ctrl->value & 0xff, &error);
		tvp5147_write_err(sd, TVP5147_B_FINE_GAIN,
						ctrl->value & 0xff, &error);

		if (error < 0)
			return error;

		/* Set only after knowing there is no error */
		device->gain = ctrl->value & 0xff;
		return 0;
	default:
		return -EINVAL;
	}
}

/*
 * tvp5147_queryctrl() - Query a control
 * @sd: ptr to v4l2_subdev struct
 * @qc: ptr to v4l2_queryctrl struct
 *
 * Query a control of a TVP5147 decoder device.
 * Returns zero when successful or -EINVAL if register read fails.
 */
static int tvp5147_queryctrl(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc)
{
	switch (qc->id) {
	case V4L2_CID_GAIN:
		/*
		 * Gain is supported [0-255, default=0, step=1]
		 */
		return v4l2_ctrl_query_fill(qc, 0, 255, 1, 0);
	default:
		return -EINVAL;
	}
}

/*
 * tvp5147_mbus_fmt() - V4L2 decoder interface handler for try/s/g_mbus_fmt
 * @sd: pointer to standard V4L2 sub-device structure
 * @f: pointer to mediabus format structure
 *
 * Negotiate the image capture size and mediabus format.
 * There is only one possible format, so this single function works for
 * get, set and try.
 */
static int tvp5147_mbus_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *f)/*TODO*/
{
	struct tvp5147 *device = to_tvp5147(sd);
	struct v4l2_dv_enum_preset e_preset;
	int error;

	/* Calculate height and width based on current standard */
	error = v4l_fill_dv_preset_info(device->current_preset->preset, &e_preset);
	if (error)
		return error;

	f->width = e_preset.width;
	f->height = e_preset.height;
	f->code = V4L2_MBUS_FMT_YUYV10_1X20;
	f->field = device->current_preset->scanmode;
	f->colorspace = device->current_preset->color_space;

	v4l2_dbg(1, debug, sd, "MBUS_FMT: Width - %d, Height - %d",
			f->width, f->height);
	return 0;
}

/*
 * tvp5147_query_dv_preset() - query DV preset
 * @sd: pointer to standard V4L2 sub-device structure
 * @qpreset: standard V4L2 v4l2_dv_preset structure
 *
 * Returns the current DV preset by TVP5147. If no active input is
 * detected, returns -EINVAL
 */
static int tvp5147_query_dv_preset(struct v4l2_subdev *sd,
						struct v4l2_dv_preset *qpreset)
{
	const struct tvp5147_preset_definition *presets = tvp5147_presets;
	struct tvp5147 *device;
	u8 progressive;
	u32 lpfr;
	u32 cpln;
	int error = 0;
	u8 lpf_lsb;
	u8 lpf_msb;
	u8 cpl_lsb;
	u8 cpl_msb;
	int index;
	v4l2_info(sd, "pass %s(%d)\n", __func__, __LINE__);
	device = to_tvp5147(sd);

	/* Read standards from device registers */
	tvp5147_read_err(sd, TVP5147_L_FRAME_STAT_LSBS, &lpf_lsb, &error);
	tvp5147_read_err(sd, TVP5147_L_FRAME_STAT_MSBS, &lpf_msb, &error);

	if (error < 0)
		return error;

	tvp5147_read_err(sd, TVP5147_CLK_L_STAT_LSBS, &cpl_lsb, &error);
	tvp5147_read_err(sd, TVP5147_CLK_L_STAT_MSBS, &cpl_msb, &error);

	if (error < 0)
		return error;

	/* Get lines per frame, clocks per line and interlaced/progresive */
	lpfr = lpf_lsb | ((TVP5147_CL_MASK & lpf_msb) << TVP5147_CL_SHIFT);
	cpln = cpl_lsb | ((TVP5147_CL_MASK & cpl_msb) << TVP5147_CL_SHIFT);
	progressive = (lpf_msb & TVP5147_INPR_MASK) >> TVP5147_IP_SHIFT;

	/* Do checking of video modes */
	for (index = 0; index < NUM_PRESETS; index++, presets++)
		if (lpfr  == presets->lines_per_frame &&
			progressive == presets->progressive) {
			if (presets->cpl_min == 0xffff)
				break;
			if (cpln >= presets->cpl_min && cpln <= presets->cpl_max)
				break;
		}

	if (index == NUM_PRESETS) {
		v4l2_dbg(1, debug, sd, "detection failed: lpf = %x, cpl = %x\n",
								lpfr, cpln);
		/* Could not detect a signal, so return the 'invalid' preset */
		qpreset->preset = V4L2_DV_INVALID;
		return 0;
	}

	/* Set values in found preset */
	qpreset->preset = presets->preset;

	/* Update lines per frame and clocks per line info */
	v4l2_dbg(1, debug, sd, "detected preset: %d\n", presets->preset);
	return 0;
}

#ifdef CONFIG_VIDEO_ADV_DEBUG
/*
 * tvp5147_g_register() - Get the value of a register
 * @sd: ptr to v4l2_subdev struct
 * @reg: ptr to v4l2_dbg_register struct
 *
 * Get the value of a TVP5147 decoder device register.
 * Returns zero when successful, -EINVAL if register read fails or
 * access to I2C client fails, -EPERM if the call is not allowed
 * by diabled CAP_SYS_ADMIN.
 */
static int tvp5147_g_register(struct v4l2_subdev *sd,
						struct v4l2_dbg_register *reg)
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);
	u8 val;
	int ret;

	if (!v4l2_chip_match_i2c_client(client, &reg->match))
		return -EINVAL;
	if (!capable(CAP_SYS_ADMIN))
		return -EPERM;

	ret = tvp5147_read(sd, reg->reg & 0xff, &val);
	reg->val = val;
	return ret;
}

/*
 * tvp5147_s_register() - set a control
 * @sd: ptr to v4l2_subdev struct
 * @reg: ptr to v4l2_dbg_register struct
 *
 * Get the value of a TVP5147 decoder device register.
 * Returns zero when successful, -EINVAL if register read fails or
 * -EPERM if call not allowed.
 */
static int tvp5147_s_register(struct v4l2_subdev *sd,
						struct v4l2_dbg_register *reg)
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);

	if (!v4l2_chip_match_i2c_client(client, &reg->match))
		return -EINVAL;
	if (!capable(CAP_SYS_ADMIN))
		return -EPERM;

	return tvp5147_write(sd, reg->reg & 0xff, reg->val & 0xff);
}
#endif

/*
 * tvp5147_enum_mbus_fmt() - Enum supported mediabus formats
 * @sd: pointer to standard V4L2 sub-device structure
 * @index: format index
 * @code: pointer to mediabus format
 *
 * Enumerate supported mediabus formats.
 */

static int tvp5147_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned index,
					enum v4l2_mbus_pixelcode *code)
{
	/* Check requested format index is within range */
	if (index)
		return -EINVAL;
	*code = V4L2_MBUS_FMT_YUYV10_1X20;
	return 0;
}

/*
 * tvp5147_s_stream() - V4L2 decoder i/f handler for s_stream
 * @sd: pointer to standard V4L2 sub-device structure
 * @enable: streaming enable or disable
 *
 * Sets streaming to enable or disable, if possible.
 */
static int tvp5147_s_stream(struct v4l2_subdev *sd, int enable)
{
	struct tvp5147 *device = to_tvp5147(sd);
	int error = 0;

	if (device->streaming == enable)
		return 0;

	if (enable) {
		/* Set output state on (low impedance means stream on) */
		error = tvp5147_write(sd, TVP5147_MISC_CTL_2, 0x00);
		device->streaming = enable;
	} else {
		/* Set output state off (high impedance means stream off) */
		error = tvp5147_write(sd, TVP5147_MISC_CTL_2, 0x03);
		if (error)
			v4l2_dbg(1, debug, sd, "Unable to stop streaming\n");

		device->streaming = enable;
	}

	return error;
}

/*
 * tvp5147_log_status() - Print information about register settings
 * @sd: ptr to v4l2_subdev struct
 *
 * Log register values of a TVP5147 decoder device.
 * Returns zero or -EINVAL if read operation fails.
 */
static int tvp5147_log_status(struct v4l2_subdev *sd)
{
	const struct tvp5147_preset_definition *presets = tvp5147_presets;
	struct tvp5147 *device = to_tvp5147(sd);
	struct v4l2_dv_enum_preset e_preset;
	struct v4l2_dv_preset detected;
	int i;

	detected.preset = V4L2_DV_INVALID;
	/* Find my current standard*/
	tvp5147_query_dv_preset(sd, &detected);

	/* Print standard related code values */
	for (i = 0; i < NUM_PRESETS; i++, presets++)
		if (presets->preset == detected.preset)
			break;

	if (v4l_fill_dv_preset_info(device->current_preset->preset, &e_preset))
		return -EINVAL;

	v4l2_info(sd, "Selected DV Preset: %s\n", e_preset.name);
	v4l2_info(sd, "   Pixels per line: %u\n", e_preset.width);
	v4l2_info(sd, "   Lines per frame: %u\n\n", e_preset.height);
	if (i == NUM_PRESETS) {
		v4l2_info(sd, "Detected DV Preset: None\n");
	} else {
		if (v4l_fill_dv_preset_info(presets->preset, &e_preset))
			return -EINVAL;
		v4l2_info(sd, "Detected DV Preset: %s\n", e_preset.name);
		v4l2_info(sd, "  Pixels per line: %u\n", e_preset.width);
		v4l2_info(sd, "  Lines per frame: %u\n\n", e_preset.height);
	}
	v4l2_info(sd, "Streaming enabled: %s\n",
					device->streaming ? "yes" : "no");

	/* Print the current value of the gain control */
	v4l2_info(sd, "Gain: %u\n", device->gain);

	return 0;
}

/*
 * tvp5147_enum_dv_presets() - Enum supported digital video formats
 * @sd: pointer to standard V4L2 sub-device structure
 * @preset: pointer to format struct
 *
 * Enumerate supported digital video formats.
 */
static int tvp5147_enum_dv_presets(struct v4l2_subdev *sd,
		struct v4l2_dv_enum_preset *preset)
{
	/* Check requested format index is within range */
	if (preset->index >= NUM_PRESETS)
		return -EINVAL;

	return v4l_fill_dv_preset_info(tvp5147_presets[preset->index].preset, preset);
}

/* V4L2 core operation handlers */
static const struct v4l2_subdev_core_ops tvp5147_core_ops = {
	//.g_chip_ident = tvp5147_g_chip_ident,
	.log_status = tvp5147_log_status,
	.g_ctrl = tvp5147_g_ctrl,
	.s_ctrl = tvp5147_s_ctrl,
	.queryctrl = tvp5147_queryctrl,
#ifdef CONFIG_VIDEO_ADV_DEBUG
	.g_register = tvp5147_g_register,
	.s_register = tvp5147_s_register,
#endif
};

/* Specific video subsystem operation handlers */
static const struct v4l2_subdev_video_ops tvp5147_video_ops = {
	.enum_dv_presets = tvp5147_enum_dv_presets,
	.s_dv_preset = tvp5147_s_dv_preset,
	.query_dv_preset = tvp5147_query_dv_preset,
	.s_stream = tvp5147_s_stream,
	.g_mbus_fmt = tvp5147_mbus_fmt,
	.try_mbus_fmt = tvp5147_mbus_fmt,
	.s_mbus_fmt = tvp5147_mbus_fmt,
	.enum_mbus_fmt = tvp5147_enum_mbus_fmt,
};

/* V4L2 top level operation handlers */
static const struct v4l2_subdev_ops tvp5147_ops = {
	.core = &tvp5147_core_ops,
	.video = &tvp5147_video_ops,
};

static struct tvp5147 tvp5147_dev = {
	.streaming = 0,
	.current_preset = tvp5147_presets,
	.gain = 0,
};

/*
 * tvp5147_probe - Probe a TVP5147 device
 * @c: ptr to i2c_client struct
 * @id: ptr to i2c_device_id struct
 *
 * Initialize the TVP5147 device
 * Returns zero when successful, -EINVAL if register read fails or
 * -EIO if i2c access is not available.
 */
static int tvp5147_probe(struct i2c_client *c, const struct i2c_device_id *id)
{
	struct v4l2_subdev *sd;
	struct tvp5147 *device;
	struct v4l2_dv_preset preset;
	int polarity_a;
	int polarity_b;
	u8 revision;

	int error;

	/* Check if the adapter supports the needed features */
	if (!i2c_check_functionality(c->adapter,
		I2C_FUNC_SMBUS_READ_BYTE | I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
		return -EIO;

	if (!c->dev.platform_data) {
		v4l_err(c, "No platform data!!\n");
		return -ENODEV;
	}

	device = kmalloc(sizeof(struct tvp5147), GFP_KERNEL);

	if (!device)
		return -ENOMEM;

	*device = tvp5147_dev;
	sd = &device->sd;
	device->pdata = c->dev.platform_data;

	/* Tell v4l2 the device is ready */
	v4l2_i2c_subdev_init(sd, c, &tvp5147_ops);
	v4l_info(c, "tvp5147 found @ 0x%02x (%s)\n",
					c->addr, c->adapter->name);

	error = tvp5147_read(sd, TVP5147_CHIP_REV, &revision);
	if (error < 0)
		goto found_error;

	/* Get revision number */
	v4l2_info(sd, "Rev. %02x detected.\n", revision);
	if (revision != 0x02)
		v4l2_info(sd, "Unknown revision detected.\n");

	/* Initializes TVP5147 to its default values */
	error = tvp5147_write_inittab(sd, tvp5147_init_default);

	if (error < 0)
		goto found_error;

	/* Set polarity information after registers have been set */
	polarity_a = 0x20 | device->pdata->hs_polarity << 5
			| device->pdata->vs_polarity << 2;
	error = tvp5147_write(sd, TVP5147_SYNC_CTL_1, polarity_a);
	if (error < 0)
		goto found_error;

	polarity_b = device->pdata->fid_polarity << 2
			| device->pdata->sog_polarity << 1
			| device->pdata->clk_polarity;
	error = tvp5147_write(sd, TVP5147_MISC_CTL_3, polarity_b);
	if (error < 0)
		goto found_error;

	/* Set registers according to default video mode */
	preset.preset = device->current_preset->preset;
	error = tvp5147_s_dv_preset(sd, &preset);

found_error:
	if (error < 0)
		kfree(device);

	return error;
}

/*
 * tvp5147_remove - Remove TVP5147 device support
 * @c: ptr to i2c_client struct
 *
 * Reset the TVP5147 device
 * Returns zero.
 */
static int tvp5147_remove(struct i2c_client *c)
{
	struct v4l2_subdev *sd = i2c_get_clientdata(c);
	struct tvp5147 *device = to_tvp5147(sd);

	v4l2_dbg(1, debug, sd, "Removing tvp5147 adapter"
				"on address 0x%x\n", c->addr);

	v4l2_device_unregister_subdev(sd);
	kfree(device);
	return 0;
}

/* I2C Device ID table */
static const struct i2c_device_id tvp5147_id[] = {
	{ "tvp5147", 0 },
	{ }
};
MODULE_DEVICE_TABLE(i2c, tvp5147_id);

/* I2C driver data */
static struct i2c_driver tvp5147_driver = {
	.driver = {
		.owner = THIS_MODULE,
		.name = TVP5147_MODULE_NAME,
	},
	.probe = tvp5147_probe,
	.remove = tvp5147_remove,
	.id_table = tvp5147_id,
};

/*
 * tvp5147_init - Initialize driver via I2C interface
 *
 * Register the TVP5147 driver.
 * Return 0 on success or error code on failure.
 */
static int __init tvp5147_init(void)
{
	return i2c_add_driver(&tvp5147_driver);
}

/*
 * tvp5147_exit - Remove driver via I2C interface
 *
 * Unregister the TVP5147 driver.
 * Returns nothing.
 */
static void __exit tvp5147_exit(void)
{
	i2c_del_driver(&tvp5147_driver);
}

module_init(tvp5147_init);
module_exit(tvp5147_exit);

#!/bin/sh

PATH_TO_TOOLCHAIN=/home/hieg/Sourcery/Sourcery_G++_Lite

make ARCH=arm CROSS_COMPILE=${PATH_TO_TOOLCHAIN}/bin/arm-none-linux-gnueabi- ti8148_evm_defconfig
make ARCH=arm CROSS_COMPILE=${PATH_TO_TOOLCHAIN}/bin/arm-none-linux-gnueabi- uImage

#make ARCH=arm CROSS_COMPILE=${PATH_TO_TOOLCHAIN}/bin/arm-none-linux-gnueabi- menuconfig
make ARCH=arm CROSS_COMPILE=${PATH_TO_TOOLCHAIN}/bin/arm-none-linux-gnueabi- modules

sudo cp /home/hieg/ti-ezsdk_dm814x-evm_5_05_02_00/board-support/linux-2.6.37-psp04.04.00.01/arch/arm/boot/uImage /srv/tftp/
cd /srv/tftp
sudo chmod 777 uImage


#modules

sudo cp /home/hieg/ti-ezsdk_dm814x-evm_5_05_02_00/board-support/linux-2.6.37-psp04.04.00.01/drivers/video/ti81xx/ti81xxfb/ti81xxfb.ko /home/hieg/targetfs/lib/modules/2.6.37/kernel/drivers/video/ti81xx/ti81xxfb/
sudo cp /home/hieg/ti-ezsdk_dm814x-evm_5_05_02_00/board-support/linux-2.6.37-psp04.04.00.01/drivers/video/ti81xx/ti81xxhdmi/ti81xxhdmi.ko /home/hieg/targetfs/lib/modules/2.6.37/kernel/drivers/video/ti81xx/ti81xxhdmi/
sudo cp /home/hieg/ti-ezsdk_dm814x-evm_5_05_02_00/board-support/linux-2.6.37-psp04.04.00.01/drivers/media/video/ti81xx/ti81xxvin.ko /home/hieg/targetfs/lib/modules/2.6.37/kernel/drivers/media/video/ti81xx/
sudo cp /home/hieg/ti-ezsdk_dm814x-evm_5_05_02_00/board-support/linux-2.6.37-psp04.04.00.01/drivers/media/video/ti81xx/ti81xxvo.ko /home/hieg/targetfs/lib/modules/2.6.37/kernel/drivers/media/video/ti81xx/
sudo cp /home/hieg/ti-ezsdk_dm814x-evm_5_05_02_00/board-support/linux-2.6.37-psp04.04.00.01/drivers/media/video/tvp514x.ko /home/hieg/targetfs/lib/modules/2.6.37/kernel/drivers/media/video/
sudo cp /home/hieg/ti-ezsdk_dm814x-evm_5_05_02_00/board-support/linux-2.6.37-psp04.04.00.01/drivers/media/video/tvp7002.ko /home/hieg/targetfs/lib/modules/2.6.37/kernel/drivers/media/video/
sudo cp /home/hieg/ti-ezsdk_dm814x-evm_5_05_02_00/board-support/linux-2.6.37-psp04.04.00.01/drivers/video/ti81xx/vpss/vpss.ko /home/hieg/targetfs/lib/modules/2.6.37/kernel/drivers/video/ti81xx/vpss/

#!/bin/sh

cd /home/root/VideoCapture

/etc/init.d/matrix-gui-e  stop
/etc/init.d/pvr-init stop
/etc/init.d/load-hd-firmware.sh stop

insmod /lib/modules/2.6.37/kernel/drivers/media/video/tvp514x.ko debug=1
/usr/share/ti/ti-media-controller-utils/load-hd-v4l2-firmware.sh start

./saMarc
dmesg
lsmod
./saLoopBack

PM: Removing info for No Bus:bccat0
PM: Removing info for No Bus:pvrsrvkm
PM: Removing info for platform:pvrsrvkm
PM: Removing info for No Bus:tlc59108-bl
hdmi: Enter DSS_HDMI_CORE_SW_RESET_ASSERT ()
hdmi: Enter HDMI_W1_StopVideoFrame()
hdmi: *** Set PHY power mode to 0
hdmi: *** Set PHY power mode to 0
PM: Removing info for No Bus:TI81XX_HDMI
PM: Removing info for No Bus:fb0
PM: Removing info for No Bus:fb1
PM: Removing info for No Bus:fb2
PM: Removing info for No Bus:syslinkipc_MessageQ
PM: Removing info for No Bus:syslinkipc_GateMP
PM: Removing info for No Bus:syslinkipc_ListMP
PM: Removing info for No Bus:syslinkipc_HeapMemMP
PM: Removing info for No Bus:syslinkipc_HeapBufMP
PM: Removing info for No Bus:syslinkipc_SharedRegion
PM: Removing info for No Bus:syslinkipc_NameServer
PM: Removing info for No Bus:syslinkipc_MultiProc
PM: Removing info for No Bus:syslinkipc_Notify
PM: Removing info for No Bus:syslinkipc_FrameQ
PM: Removing info for No Bus:syslinkipc_FrameQBufMgr
PM: Removing info for No Bus:syslinkipc_RingIO
PM: Removing info for No Bus:syslinkipc_RingIOShm
PM: Removing info for No Bus:syslinkipc_ClientNotifyMgr
PM: Removing info for No Bus:syslinkipc_SyslinkMemMgr
PM: Removing info for No Bus:syslinkipc_ProcMgr
PM: Removing info for No Bus:syslinkipc_Ipc
PM: Removing info for No Bus:syslinkipc_Osal
Removed syslink kernel module
SysLink version : 2.20.02.20
SysLink module created on Date:Dec 26 2012 Time:18:39:49
PM: Adding info for No Bus:syslinkipc_Osal
PM: Adding info for No Bus:syslinkipc_Ipc
PM: Adding info for No Bus:syslinkipc_ProcMgr
PM: Adding info for No Bus:syslinkipc_Notify
PM: Adding info for No Bus:syslinkipc_MultiProc
PM: Adding info for No Bus:syslinkipc_NameServer
PM: Adding info for No Bus:syslinkipc_SharedRegion
PM: Adding info for No Bus:syslinkipc_HeapBufMP
PM: Adding info for No Bus:syslinkipc_HeapMemMP
PM: Adding info for No Bus:syslinkipc_ListMP
PM: Adding info for No Bus:syslinkipc_GateMP
PM: Adding info for No Bus:syslinkipc_MessageQ
PM: Adding info for No Bus:syslinkipc_SyslinkMemMgr
PM: Adding info for No Bus:syslinkipc_ClientNotifyMgr
PM: Adding info for No Bus:syslinkipc_FrameQBufMgr
PM: Adding info for No Bus:syslinkipc_FrameQ
PM: Adding info for No Bus:syslinkipc_RingIO
PM: Adding info for No Bus:syslinkipc_RingIOShm
VPSS_FVID2: M3 firmware version 0x1000145 is newer,driver may not work properly.
TI81XXFB  : ti81xxfb_init
TI81XXFB  : create 3 fbs
TI81XXFB  : fb_infos(3) allocated.
TI81XXFB  : vram 0:40M,1:1M,2:1M
TI81XXFB  : fb 0 size 41943040
TI81XXFB  : fb 1 size 1048576
TI81XXFB  : fb 2 size 1048576
TI81XXFB  : allocating 41943040 bytes for fb 0
TI81XXFB  : allocated VRAM paddr 8ce00000, vaddr d1000000
TI81XXFB  : allocating 1048576 bytes for fb 1
TI81XXFB  : allocated VRAM paddr 8f600000, vaddr d3800000
TI81XXFB  : allocating 1048576 bytes for fb 2
TI81XXFB  : allocated VRAM paddr 8f700000, vaddr d3900000
TI81XXFB  : region0 phys 8ce00000 virt d1000000 size=41943040
TI81XXFB  : region1 phys 8f600000 virt d3800000 size=1048576
TI81XXFB  : region2 phys 8f700000 virt d3900000 size=1048576
TI81XXFB  : fb memory allocated.
TI81XXFB  : clut mem allocated.
TI81XXFB  : check_fb_var
TI81XXFB  : xres = 1920, yres = 1080, vxres = 1920, vyres = 1080,xoffset = 0, yoffset = 0
TI81XXFB  : set_fb_fix
TI81XXFB  : check_fb_var
TI81XXFB  : can't fit fb memory, reducing y
TI81XXFB  : xres = 1920, yres = 136, vxres = 1920, vyres = 136,xoffset = 0, yoffset = 0
TI81XXFB  : set_fb_fix
TI81XXFB  : check_fb_var
TI81XXFB  : can't fit fb memory, reducing y
TI81XXFB  : xres = 720, yres = 364, vxres = 720, vyres = 364,xoffset = 0, yoffset = 0
TI81XXFB  : set_fb_fix
TI81XXFB  : fb_infos initialized
PM: Adding info for No Bus:fb0
PM: Adding info for No Bus:fb1
PM: Adding info for No Bus:fb2
TI81XXFB  : framebuffers registered
TI81XXFB  : fbs sysfs created
TI81XXFB  : Opening fb0
TI81XXFB  : check_var(0)
TI81XXFB  : check_fb_var
TI81XXFB  : xres = 800, yres = 480, vxres = 800, vyres = 480,xoffset = 0, yoffset = 0
TI81XXFB  : set_var(0)
TI81XXFB  : set_fb_fix
TI81XXFB  : pan_display(0)
TI81XXFB  : setcamp(0)
TI81XXFB  : clut not same ,set
TI81XXFB  : Closing fb0
drivers/media/video/ti81xx/ti81xxvid_main.c ti81xx_vidout_setup_video_bufs
t81xx_vidout t81xx_vidout: VIDOUT0: buf0: va: 0xc4800000 pa: 0x84800000 size 0x400000
drivers/media/video/ti81xx/ti81xxvid_main.c ti81xx_vidout_setup_video_bufs
t81xx_vidout t81xx_vidout: VIDOUT0: buf1: va: 0xc4400000 pa: 0x84400000 size 0x400000
drivers/media/video/ti81xx/ti81xxvid_main.c ti81xx_vidout_setup_video_bufs
t81xx_vidout t81xx_vidout: VIDOUT0: buf2: va: 0xc4000000 pa: 0x84000000 size 0x400000
PM: Adding info for No Bus:video1
drivers/media/video/ti81xx/ti81xxvid_main.c ti81xxvid_init
t81xx_vidout t81xx_vidout: VIDOUT0: init video
drivers/media/video/ti81xx/ti81xxvid_main.c video_mode_to_vpss_mode
t81xx_vidout t81xx_vidout: VIDOUT0: data format 1
drivers/media/video/ti81xx/ti81xxvid_main.c ti81xxvid_setup_video
t81xx_vidout t81xx_vidout: VIDOUT0: enable=0 width=1920
 height=1080 color_mode=1
pos=0x0 out_width=1920 out_height=1080 screen_width=3840 crop=0
t81xx_vidout t81xx_vidout: VIDOUT0: apply_changes failed
drivers/media/video/ti81xx/ti81xxvid_main.c ti81xx_vidout_setup_video_bufs
t81xx_vidout t81xx_vidout: VIDOUT1: buf0: va: 0xc3c00000 pa: 0x83c00000 size 0x400000
drivers/media/video/ti81xx/ti81xxvid_main.c ti81xx_vidout_setup_video_bufs
t81xx_vidout t81xx_vidout: VIDOUT1: buf1: va: 0xc3800000 pa: 0x83800000 size 0x400000
drivers/media/video/ti81xx/ti81xxvid_main.c ti81xx_vidout_setup_video_bufs
t81xx_vidout t81xx_vidout: VIDOUT1: buf2: va: 0xc3400000 pa: 0x83400000 size 0x400000
PM: Adding info for No Bus:video2
drivers/media/video/ti81xx/ti81xxvid_main.c ti81xxvid_init
t81xx_vidout t81xx_vidout: VIDOUT1: init video
drivers/media/video/ti81xx/ti81xxvid_main.c video_mode_to_vpss_mode
t81xx_vidout t81xx_vidout: VIDOUT1: data format 1
drivers/media/video/ti81xx/ti81xxvid_main.c ti81xxvid_setup_video
t81xx_vidout t81xx_vidout: VIDOUT1: enable=0 width=800
 height=480 color_mode=1
pos=0x0 out_width=800 out_height=480 screen_width=1600 crop=0
t81xx_vidout t81xx_vidout: VIDOUT1: apply_changes failed
drivers/media/video/ti81xx/ti81xxvid_main.c ti81xx_vidout_setup_video_bufs
t81xx_vidout t81xx_vidout: VIDOUT2: buf0: va: 0xca500000 pa: 0x8a500000 size 0xca800
drivers/media/video/ti81xx/ti81xxvid_main.c ti81xx_vidout_setup_video_bufs
t81xx_vidout t81xx_vidout: VIDOUT2: buf1: va: 0xca700000 pa: 0x8a700000 size 0xca800
drivers/media/video/ti81xx/ti81xxvid_main.c ti81xx_vidout_setup_video_bufs
t81xx_vidout t81xx_vidout: VIDOUT2: buf2: va: 0xc3000000 pa: 0x83000000 size 0xca800
PM: Adding info for No Bus:video3
drivers/media/video/ti81xx/ti81xxvid_main.c ti81xxvid_init
t81xx_vidout t81xx_vidout: VIDOUT2: init video
drivers/media/video/ti81xx/ti81xxvid_main.c video_mode_to_vpss_mode
t81xx_vidout t81xx_vidout: VIDOUT2: data format 1
drivers/media/video/ti81xx/ti81xxvid_main.c ti81xxvid_setup_video
t81xx_vidout t81xx_vidout: VIDOUT2: enable=0 width=720
 height=480 color_mode=1
pos=0x0 out_width=720 out_height=480 screen_width=1440 crop=0
t81xx_vidout t81xx_vidout: VIDOUT2: apply_changes failed
drivers/media/video/ti81xx/ti81xxvin_main.c, ti81xxvin_probe
PM: Adding info for No Bus:video0
PM: Adding info for No Bus:video4
PM: Adding info for No Bus:video5
PM: Adding info for No Bus:video6
tvp514x 
drivers/media/video/v4l2-common.c, v4l2_i2c_new_subdev_board
PM: Adding info for i2c:1-005c
drivers/media/video/tvp514x.c, tvp514x_probe
drivers/media/video/tvp514x.c tvp514x_probe
tvp514x 1-005c: tvp514x 1-005c decoder driver registered 
drivers/media/video/tvp514x.c, tvp514x_s_config
drivers/media/video/tvp514x.c, tvp514x_s_stream
0 3 1 
drivers/media/video/tvp514x.c tvp514x_write_reg
tvp514x 1-005c: Write: retry --- 0
drivers/media/video/tvp514x.c tvp514x_write_reg
tvp514x 1-005c: Write: retry --- 1
drivers/media/video/tvp514x.c tvp514x_write_reg
tvp514x 1-005c: Write: retry --- 2
drivers/media/video/tvp514x.c tvp514x_write_reg
tvp514x 1-005c: Write: retry --- 3
drivers/media/video/tvp514x.c tvp514x_write_reg
tvp514x 1-005c: Write: retry --- 4
drivers/media/video/tvp514x.c tvp514x_write_regs
tvp514x 1-005c: Write failed. Err[-121]
drivers/media/video/tvp514x.c tvp514x_s_stream
tvp514x 1-005c: Unable to turn on decoder !!!!!!
drivers/media/video/tvp514x.c tvp514x_read_reg
tvp514x 1-005c: Read: retry ... 0
drivers/media/video/tvp514x.c tvp514x_read_reg
tvp514x 1-005c: Read: retry ... 1
drivers/media/video/tvp514x.c tvp514x_read_reg
tvp514x 1-005c: Read: retry ... 2
drivers/media/video/tvp514x.c tvp514x_read_reg
tvp514x 1-005c: Read: retry ... 3
drivers/media/video/tvp514x.c tvp514x_read_reg
tvp514x 1-005c: Read: retry ... 4
drivers/media/video/tvp514x.c tvp514x_s_config
tvp514x 1-005c: Unable to query std
drivers/media/video/ti81xx/ti81xxvin_main.c ti81xxvin_probe
ti81xxvin ti81xxvin: registered sub device tvp5147m1
drivers/media/video/ti81xx/ti81xxvin_main.c ti81xxvin_probe
ti81xxvin ti81xxvin: TI81xx HDVPSS Capture driver initialized
FIN de ti81xxvin_probe
TI81XXFB  : Opening fb0
TI81XXFB  : check_var(0)
TI81XXFB  : check_fb_var
TI81XXFB  : xres = 800, yres = 480, vxres = 800, vyres = 480,xoffset = 0, yoffset = 0
TI81XXFB  : set_var(0)
TI81XXFB  : set_fb_fix
TI81XXFB  : pan_display(0)
TI81XXFB  : setcamp(0)
TI81XXFB  : Closing fb0
HDMI W1 rev 4.0
HDMI CEC Spec version 1.2
PM: Adding info for No Bus:TI81XX_HDMI
hdmi: Enter HDMI_W1_StopVideoFrame()
hdmi: *** Set PHY power mode to 1
hdmi: *** Set PHY power mode to 2
I2C No Ack

hdmi: Enter HDMI_W1_GlobalInitVars()
hdmi: Enter HDMI_Core_GlobalInitVars()
hdmi: Enter HDMI_W1_ConfigVideoResolutionTiming()
hdmi: Enter HDMI_W1_ConfigVideoInterface()
hdmi: HDMI_WP_AUDIO_CFG = 0x1030006
hdmi: HDMI_WP_AUDIO_CFG2 = 0x20c0
hdmi: HDMI_WP_AUDIO_CTRL = 0x20
hdmi: Enter DSS_HDMI_CORE_SW_RESET_ASSERT ()
hdmi: Enter DSS_HDMI_CORE_POWER_DOWN_DISABLE()
hdmi: Enter DSS_HDMI_CORE_SW_RESET_RELEASE()
hdmi: Enter HDMI_W1_StartVideoFrame  ()
hdmi: Irqenable 60000011
hdmi: 40 hpd
PM: Adding info for No Bus:tlc59108-bl
ti81xxvin ti81xxvin: ti81xxvin_open
ti81xxvin ti81xxvin: ti81xxvin_open
drivers/media/video/ti81xx/ti81xxvin_main.c vidioc_enum_input
ti81xxvin ti81xxvin: Invalid input index
ti81xxvin ti81xxvin: ti81xxvin_open
ti81xxvin ti81xxvin: ti81xxvin_open
drivers/media/video/ti81xx/ti81xxvin_main.c vidioc_enum_input
ti81xxvin ti81xxvin: Invalid input index
ti81xxvin ti81xxvin: ti81xxvin_release
ti81xxvin ti81xxvin: Failed to del timer
ti81xxvin ti81xxvin: ti81xxvin_release
ti81xxvin ti81xxvin: Failed to del timer
ti81xxvin ti81xxvin: ti81xxvin_release
ti81xxvin ti81xxvin: Failed to del timer
ti81xxvin ti81xxvin: ti81xxvin_release
ti81xxvin ti81xxvin: Failed to del timer
ti81xxvin ti81xxvin: ti81xxvin_open
hdmi: Enter DSS_HDMI_CORE_SW_RESET_ASSERT ()
hdmi: Enter HDMI_W1_StopVideoFrame()
hdmi: *** Set PHY power mode to 0
hdmi: *** Set PHY power mode to 0
drivers/media/video/ti81xx/ti81xxvin_main.c, vidioc_query_dv_preset
ti81xxvin ti81xxvin: vidioc_query_dv_preset
drivers/media/video/tvp514x.c tvp514x_read_reg
tvp514x 1-005c: Read: retry ... 0
drivers/media/video/tvp514x.c tvp514x_read_reg
tvp514x 1-005c: Read: retry ... 1
drivers/media/video/tvp514x.c tvp514x_read_reg
tvp514x 1-005c: Read: retry ... 2
drivers/media/video/tvp514x.c tvp514x_read_reg
tvp514x 1-005c: Read: retry ... 3
drivers/media/video/tvp514x.c tvp514x_read_reg
tvp514x 1-005c: Read: retry ... 4
TVP514x: unkown video standard: -121
drivers/media/video/ti81xx/ti81xxvin_main.c vidioc_query_dv_preset
ti81xxvin ti81xxvin: Failed to set dv format for sub devices
ti81xxvin ti81xxvin: ti81xxvin_release
ti81xxvin ti81xxvin: Failed to del timer