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Interrupt clear & set

Anonymous
Anonymous

Hi All,

 

I would like to ask a question on Interrupt Controller of Davinci processors.

 

Among the interrupt controller registers, three types of registers are very important:

1.    EVTFLAG[3:0]

2.    EVTCLR[3:0]

3.    EVTSET[3:0]

 

In the first line of page 159 of SPRU871k, TMS320C64x+ DSP Megamodule Reference Guide, it is said that event flags retain their values, and in the following description for EVGCLR and EVGSET it is said that these clearing or setting these two registers is the way to change corresponding EVTFLAG value and its design purpose is to avoid potential race conditions.

 

It did not say what happens after setting a particular EVTCLR or EVTSET. If they are also retained like EVTFLAG, then there will be some conflicting conditions. For example,

1.    First, EVTCLR[x] is set to 1, and retained

2.    Then, EVTSET[x] is set to 1 and retained

 

Then in the following clock cycles there will be a demand to both clear and set EVTFLAG[x], which is a conflict.

 

So although the manual didn’t say, it should be that EVTCLR and EVTSET registers will clear themselves automatically after it has been set. Is this correct?

 

I have tried to use BIOS in CCS4, but didn't find a tutorial. Is there any helpful document to get started quickly?

   

         

   

Sincerely,

Zheng

  • 0
    TI__Genius 14405 points

    I agree with you. I remember when trying it out myself, the CLR and SET registers always clear themselves out (at least it always shows "0" in the CCS window). I am pining the experts on this one to see if there is a second opinion

  • Anonymous
    0 Anonymous in reply to Paul.Yin

    Dear Paul,

     

    I also watched values of EVTCLR and EVTSET bits in CCS 4 and they are always zero even after setting them to 1. I think it is presumably because of the reason as I mentioned above.

     

    Looking forward to your follow-up answer on this.

     

    Zheng

  • 0 in reply to Paul.Yin
    TI__Genius 14405 points

    Actually, just found that the register are "write-only", so just becuase it always reads "0", I can't say it clears automatically themselves out (although I think this must be the case). Let me talk to the design people to confirm this.

  • 0 in reply to Paul.Yin
    TI__Expert 5955 points

    Adding to what Paul wrote. These are write-only registers. They read back "0". They do not clear themselves. Reading these registers does not mean anything.

    Thanks,

    Tai

  • Anonymous
    0 Anonymous in reply to Tai Nguyen

    Dear Tai,

     

    1. So strictly speaking, "reading" operation do not apply to these registers?  
    2. In the circuit level, they are not designed to be readable, and probably actually reverts to a tristate "floating" condition after each writing action, hence no meaningful value can be retrieved by any reading attempt?
    3. Technically, CCS 4 should actually show their values as 0x N/A N/A N/A N/A N/A N/A N/A N/A ? Why CCS doesn't do in this way?

     

    Zheng

  • 0 in reply to Anonymous
    TI__Expert 5955 points

    Dear Zheng,

    1. You are correct. These registers are write-only registers. A read to these registers return "0".

    2. You are correct.

    3. It should. I will forward your concern to the CCS team.

    Thanks,

    Tai

  • Anonymous
    0 Anonymous in reply to Tai Nguyen

    Dear Tai,

     

    I think this question is now resolved. Thanks very much.

     

    Zheng