Hi All,
I have another question on page 159 of SPRU871k, TMS320C64x+ DSP Megamodule Reference Guide:
On the bottom line of this page it is said:
If a new event is received during the same cycle, a clear is specified via an EVTCLRx register, the new event input takes precedence as an additional precaution against missing events.
The first half “If a new event is received during the same cycle, a clear is specified via an EVTCLRx register”, how should this be understood? Does this mean when in the clock cycle when one is writing to the clear bit EVTCLRx, and event x just happen to occur within the same cycle, when these two coexist, EVTCLRx takes precedence and the event is ignored?
If the above is true, why the second half of the sentence says that “the new event input takes precedence as an additional precaution against missing events”? It seems from this sentence that the new event x has higher priority than EVTCLRx, which contradicts the above.
Could anyone explain this to me?
Sincerely,
Zheng