hi TI experts：
I meet a little issue，I hope you can help me or give me some advise。
it ‘s about DDR3B in TCI6636（K2H）CPU: 66AK2Hx SR2.0, I using DDR3A interface IS43TR16512A-125KBLI and DDR3B with MT41K256M16TW-107，all 64 bit no ECC。now，address 0x80000000 can reading through DDR3A，but cann't reading DDR3B at 0x6000000，if I config DDR3B phy and EMIF by gel file，will be hang in CCS6 IDE，DDR3A is ok 。Hardware （DDR3A_REMAP_EN=1 ）Accroding to TI datasheet （SPRS835F） I checked clock is 666MHz，is good。CS signal is normal and voltage is 1.5V。
Refering datasheet （sprabx7）about DDR3 Initialization sequence ，as leveling error。Attach is leveling log and DDR3B gel config files。I config DDR3B using TI6636 K2H KeystoneII adbout DDR3.xlsx ERROR is “RDERR has ERROE”。DDR3B_PGSR0 = 0xB1C001FF. DDR3A_PGSR0 = 0xB00001FF , Compare wiht log between DDR3A and DDR3B.
In errata,I find Advisory21 and usagenote.6 ,more likely this issue, imporperly config PUB,Phy,EMIF. So I show config as follow:
Config DDR3B function in gel File ，I promise register,or base address and offset are OK.
/*----------------------------------------------------- DDR3B : debug, 64bit--------------------------------------------------------------------------*/
ddr3B_64bit_setup(int ECC_Enable)
{ //DDR3_PLL_333
unsigned int multiplier = 19;
unsigned int divider = 0;
unsigned int OD_val = 6;
int temp,i;
int delay = 2000;
KICK0 = 0x83E70B13;
KICK1 = 0x95A4F1E0;
// Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
do
{
read_val = DDR3B_PGSR0;
} while ((read_val&0x00000001) != 0x00000001);
//Clocks are enabled and frequency is stable---------------------------------------
//DDR3B PLL setup
GEL_TextOut ( "DDR3B PLL Setup ... \n");
DDR3BPLLCTL0 = DDR3BPLLCTL0 & 0xFF7FFFFF;
//Set ENSAT = 1
DDR3BPLLCTL1 |= 0x00000040;
// Put the PLL in PLL Mode
DDR3BPLLCTL0 |= 0x00800000;
//Program the necessary multipliers/dividers and BW adjustments
//Set the divider values
DDR3BPLLCTL0 &= ~(0x0000003F);
DDR3BPLLCTL0 |= (divider & 0x0000003F);
//Program OD[3:0] in the SECCTL register
DDR3BPLLCTL0 &= OUTPUT_DIVIDE_MASK; // clear the OD bit field
DDR3BPLLCTL0 |= ~OUTPUT_DIVIDE_MASK & (OD_val - 1) << OUTPUT_DIVIDE_OFFSET; // set the OD[3:0] bit field of PLLD to OD_val
// Set the Multipler values
DDR3BPLLCTL0 &= ~(0x0007FFC0);
DDR3BPLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 );
// Set BWADJ
temp = ((multiplier + 1) >> 1) - 1;
DDR3BPLLCTL0 &= ~(0xFF000000);
DDR3BPLLCTL0 |= ((temp << 24) & 0xFF000000);
DDR3BPLLCTL1 &= ~(0x0000000F);
DDR3BPLLCTL1 |= ((temp >> 8) & 0x0000000F);
// In PLL Controller, reset the PLL (bit 13 in DDR3BPLLCTL1 register)
DDR3BPLLCTL1 |= 0x00004000;
for(i=0;i<delay;i++);
// In DDR3PLLCTL1, write PLLRST = 0 to bring PLL out of reset
DDR3BPLLCTL1 &= ~(0x00004000);
for(i=0;i<delay;i++);
// Put the PLL in PLL Mode Switch to PLL mode
DDR3BPLLCTL0 &= ~(0x00800000); // ReSet the Bit 23
GEL_TextOut( "Lammar DDR3 PLL Setup complete, DDR3B clock now running at 666MHz.\n" );
/*------------------------------- ECO FIX -----------------------------------------*/
/*DDR3 PHY Initialization*/
// DDR3 write leveling ECO - Assert & release DDR PHY RESET after DDR PLL setup...
DDR3BPLLCTL1 = DDR3BPLLCTL1 | 0x80000000; //Assert DDR PHY reset after PLL enabled
for(i=0;i<delay;i++); //delay 1000 cycles
DDR3BPLLCTL1 = DDR3BPLLCTL1 & 0x7FFFFFFF; //Release DDR PHY reset
do
{ // Poll IDONE after resetting PHY
read_val = DDR3B_PGSR0;
} while ((read_val&0x00000001) != 0x00000001);
/*------------------------- Start PHY Configuration -------------------------------*/
// Program FRQSEL in the PLL Control Register (address offset 0x018).
DDR3B_PLLCR = 0x0005C000; //Set FRQSEL=11, for ctl_clk between 166-275MHz
// Program WLSTEP=1, IODDRM=1, and ZCKSEL in the PHY General Configuration Register 1 (address offset 0x00C).
DDR3B_PGCR1 =0x0080C507;
// Program PHY Timing Parameters Register 0-4 (address offset 0x01C - 0x02C).
DDR3B_PTR0 = 0x42C21590;
DDR3B_PTR1 = 0xD05612C0;
DDR3B_PTR2 = 0x00083DEF;
// Maintain default values of Phy Timing Parameters Register 2 in PUB
DDR3B_PTR3 = 0x0B451616;
DDR3B_PTR4 = 0x0A6E08D6;
// Program PDQ, MPRDQ, and BYTEMASK in the DRAM Configuration Register (address offset 0x044).
// All other fields must be left at their default values.
DDR3B_DCR=0x0000040B;
read_val = DDR3B_DCR;
GEL_TextOut("DDR3B_DCR = %x\n",,,,, read_val);
//Program DRAM Timing Parameters Register 0-2 (address offset 0x048 - 0x050).
DDR3B_DTPR0 = 0x85589955;//code
DDR3B_DTPR1 = 0x328573C0;
DDR3B_DTPR2 = 0x5002C200;
// Program BL=0, CL, WR, and PD=1 in the Mode Register 0 (address offset 0x054).
// All other fields must be left at their default values.
DDR3B_MR0 = 0x00001A50;
// Program DIC, RTT, and TDQS in the Mode Register 1 (address offset 0x058).
// All other fields must be left at their default values.
DDR3B_MR1 = 0x00000006;
// Program Mode Register 2 (address offset 0x05C).
DDR3B_MR2 = 0x00000050;
DDR3B_MR3 = 0x0;
// Program DTMPR=1, DTEXD, DTEXG, RANKEN=1 or 3, and RFSHDT=7 in the Data Training Configuration Register (address offset 0x068).
// All other fields must be left at their default values.
DDR3B_DTCR = 0x710035C7; //Single-rank
// Program tREFPRD=(5*tREFI/ddr_clk_period) in the PHY General Configuration Register 2 (address offset 0x08C).
//All other fields must be left at their default values.
DDR3B_PGCR2 = 0x00F065BD;
DDR3B_PGCR0 = 0xA8000E3F;
DDR3B_PGCR1 = 0x0080C507;
//Set Impedence Register and DFIPU0=1
DDR3B_ZQ0CR1 = 0x0001005D;
DDR3B_ZQ1CR1 = 0x0001005B;
DDR3B_ZQ2CR1 = 0x0001005B;
// Re-trigger PHY initialization in DDR PHY through the VBUSP interface.
// Program 0x00000033 to the PHY Initialization Register (address offset 0x004) to re-trigger PLL, ZCAL, and DCAL initialization.
DDR3B_PIR = 0x00000033;
// Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
do
{
read_val = DDR3B_PGSR0;
} while ((read_val&0x00000001) != 0x00000001);
//---------------------------------------------------------------------------------------------------------
/*DDR3B_DX2GCR = 0x7C000E81;
DDR3B_DX3GCR = 0x7C000E81;
DDR3B_DX4GCR = 0x7C000E81;
DDR3B_DX5GCR = 0x7C000E81;
DDR3B_DX6GCR = 0x7C000E81;
DDR3B_DX7GCR = 0x7C000E81;
DDR3B_DX8GCR = 0x7C000E80;*/
if(!ECC_Enable)
{
GEL_TextOut("DDR3B_DATX8_8 Front = %x\n",,,,, read_val);read_val = DDR3B_DATX8_8 ;
DDR3B_DATX8_8 = 0x7c000e80;
DDR3B_DATX8_8 = read_val & 0xFFFFFFFE; //Disable ECC byte lane
GEL_TextOut("DDR3B_DATX8_8 rear = %x\n",,,,, DDR3B_DATX8_8);
}
// Trigger DDR3 initialization and leveling/training in DDR PHY through the VBUSP interface.
// If using a 16-bit wide DDR interface, program DXEN=0 in the DATX8 2-7 General Configuration Registers (address offsets 0x240, 0x280, 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
// If using a 32-bit wide DDR interface, program DXEN=0 in the DATX8 4-7 General Configuration Registers (address offsets 0x2C0, 0x300, 0x340, and 0x380) to disable the leveling/training for the upper byte lanes.
// If ECC is not required, program DXEN=0 in the DATX8 8 General Configuration Register (address offset 0x3C0) to disable the leveling/training for the ECC byte lane.
// NOTE: Setup supports 64-bit by default, ECC enable by default.
// Program 0x0000XF81 to the PHY Initialization Register (address offset 0x004) to trigger DDR3 initialization and leveling/training sequences
DDR3B_PIR = 0x0000FF81; //WLADJ - ON
//---------------------------------------------------------------------------------------------------------
GEL_TextOut("DDR3B_leveling starting....\r\n");
// Poll for IDONE=1 in the PHY General Status Register 0 (address offset 0x010).
do {
read_val = DDR3B_PGSR0;
} while ((read_val&0x00000001) != 0x00000001);
GEL_TextOut("DDR3B_leveling over\r\n");
/* End PHY Configuration */
if(ECC_Enable)
{
GEL_TextOut("\nECC_Enable ECC_Enable ECC_Enable");
//Enable ECC
//0xB0000000: ECC_EN=1, ECC_VERIFY_EN=1, RMW_EN=1
//0x50000000: ECC_EN=1, ECC_VERIFY_EN=0, RMW_EN=1
DDR3B_ECC_CTRL = 0xB0000000;
read_val = DDR3B_ECC_CTRL;
if(read_val!=0xB0000000){
GEL_TextOut("\nIncorrect data written to DDR3B_ECC_CTRL..");
}
}
GEL_TextOut("PHY Config Complete.... \r\n");
//---------------------------------------------------------------------------------------------------------
//For single rank, EBANK field in DDR_SDCFG register needs to be programmed to 0x0.
DDR3B_SDCFG = 0x62008A62; //Single-Rank--
DDR3B_SDTIM1 = 0x125C8074;
DDR3B_SDTIM2 = 0x00001D08;
DDR3B_SDTIM3 = 0x32CDFF43;
DDR3B_SDTIM4 = 0xF43F0ADF;
//For single rank, ZQCFG needs to be programmed to 0x70073200.
DDR3B_ZQCFG = 0x70073200; //Single-Rank 0x70073200
// Program reg_initref_dis=0 in the SDRAM Refresh Control Register (address offset 0x10).
DDR3B_SDRFC = 0x00001458;//0x00000A2C
read_val = DDR3B_PGSR0;
GEL_TextOut("DDR3B_PGSR0 = %x\n",,,,, read_val);
read_val = DDR3B_PGSR1;
GEL_TextOut("DDR3B_PGSR1 = %x\n",,,,, read_val);
GEL_TextOut("DDR3B 1600 initialization complete \n");
/* End DDR3B EMIF Configuration */
}
arm_A15_0: GEL Output: DDR3B PLL Setup ...
arm_A15_0: GEL Output: Lammar DDR3 PLL Setup complete, DDR3B clock now running at 666MHz.
arm_A15_0: GEL Output: DDR3B_DCR = 0x0000040B
arm_A15_0: GEL Output: DDR3B_DATX8_8 Front = 0xB000000F
arm_A15_0: GEL Output: DDR3B_DATX8_8 rear = 0xB000000E
arm_A15_0: GEL Output: DDR3B_PGSR0 = 0xB1C001FF
arm_A15_0: GEL Output: DDR3B_PGSR1 = 0x00000000
arm_A15_0: GEL Output: DDR3B 1333 initialization complete
arm_A15_0: GEL Output: ****************************************************************************************************************
arm_A15_0: GEL Output: ********************************************************
arm_A15_0: GEL Output: ****************************************************************************************************************
arm_A15_0: GEL Output: ***************** DDR3B Leveling Errors *********************
arm_A15_0: GEL Output: PGSR0[27]: WEERR has ** No Error **
arm_A15_0: GEL Output: PGSR0[26]: REERR has ** No Error **
arm_A15_0: GEL Output: PGSR0[25]: WDERR has ** No Error **
arm_A15_0: GEL Output: PGSR0[24]: RDERR has ** Error **
arm_A15_0: GEL Output: PGSR0[23]: WLAERR has ** Error **
arm_A15_0: GEL Output: PGSR0[22]: QSGERR has ** Error **
arm_A15_0: GEL Output: PGSR0[21]: WLERR has ** No Error **
arm_A15_0: GEL Output: PGSR0[20]: ZCERR has ** No Error **
arm_A15_0: GEL Output: PGSR0[11]: WEDONE is ** Not Set **
arm_A15_0: GEL Output: PGSR0[10]: REDONE is ** Not Set **
arm_A15_0: GEL Output: PGSR0[9]: WDDONE is ** Not Set **
arm_A15_0: GEL Output: PGSR0[8]: RDDONE is ** Set **
arm_A15_0: GEL Output: PGSR0[7]: WLADONE is ** Set **
arm_A15_0: GEL Output: PGSR0[6]: QSGDONE is ** Set **
arm_A15_0: GEL Output: PGSR0[5]: WLDONE is ** Set **
arm_A15_0: GEL Output: PGSR0[4]: DIDONE is ** Set **
arm_A15_0: GEL Output: PGSR0[3]: ZCDONE is ** Not Set **
arm_A15_0: GEL Output: PGSR0[2]: DCDONE is ** Set **
arm_A15_0: GEL Output: PGSR0[1]: PLDONE is ** Set **
arm_A15_0: GEL Output: PGSR0[0]: IDONE is ** Set **
arm_A15_0: GEL Output: ********************************************************
arm_A15_0: GEL Output: Leveling Errors by Byte Lane:
arm_A15_0: GEL Output: Byte Lane 0:
arm_A15_0: GEL Output: DX0GSR2[6]: WEERR has ** No Error **
arm_A15_0: GEL Output: DX0GSR2[4]: REERR has ** No Error **
arm_A15_0: GEL Output: DX0GSR2[2]: WDERR has ** No Error **
arm_A15_0: GEL Output: DX0GSR2[0]: RDERR has ** Error **
arm_A15_0: GEL Output: DX0GSR0[25]: QSGERR on Rank1 has ** No Error **
arm_A15_0: GEL Output: DX0GSR0[24]: QSGERR on Rank0 has ** Error **
arm_A15_0: GEL Output: DX0GSR0[6]: WLERR has ** No Error **
arm_A15_0: GEL Output: Byte Lane 1:
arm_A15_0: GEL Output: DX1GSR2[6]: WEERR has ** No Error **
arm_A15_0: GEL Output: DX1GSR2[4]: REERR has ** No Error **
arm_A15_0: GEL Output: DX1GSR2[2]: WDERR has ** No Error **
arm_A15_0: GEL Output: DX1GSR2[0]: RDERR has ** Error **
arm_A15_0: GEL Output: DX1GSR0[25]: QSGERR on Rank1 has ** No Error **
arm_A15_0: GEL Output: DX1GSR0[24]: QSGERR on Rank0 has ** Error **
arm_A15_0: GEL Output: DX1GSR0[6]: WLERR has ** No Error **
arm_A15_0: GEL Output: Byte Lane 2:
arm_A15_0: GEL Output: DX2GSR2[6]: WEERR has ** No Error **
arm_A15_0: GEL Output: DX2GSR2[4]: REERR has ** No Error **
arm_A15_0: GEL Output: DX2GSR2[2]: WDERR has ** No Error **
arm_A15_0: GEL Output: DX2GSR2[0]: RDERR has ** Error **
arm_A15_0: GEL Output: DX2GSR0[25]: QSGERR on Rank1 has ** No Error **
arm_A15_0: GEL Output: DX2GSR0[24]: QSGERR on Rank0 has ** Error **
arm_A15_0: GEL Output: DX2GSR0[6]: WLERR has ** No Error **
arm_A15_0: GEL Output: Byte Lane 3:
arm_A15_0: GEL Output: DX3GSR2[6]: WEERR has ** No Error **
arm_A15_0: GEL Output: DX3GSR2[4]: REERR has ** No Error **
arm_A15_0: GEL Output: DX3GSR2[2]: WDERR has ** No Error **
arm_A15_0: GEL Output: DX3GSR2[0]: RDERR has ** Error **
arm_A15_0: GEL Output: DX3GSR0[25]: QSGERR on Rank1 has ** No Error **
arm_A15_0: GEL Output: DX3GSR0[24]: QSGERR on Rank0 has ** Error **
arm_A15_0: GEL Output: DX3GSR0[6]: WLERR has ** No Error **
arm_A15_0: GEL Output: Byte Lane 4:
arm_A15_0: GEL Output: DX4GSR2[6]: WEERR has ** No Error **
arm_A15_0: GEL Output: DX4GSR2[4]: REERR has ** No Error **
arm_A15_0: GEL Output: DX4GSR2[2]: WDERR has ** No Error **
arm_A15_0: GEL Output: DX4GSR2[0]: RDERR has ** Error **
arm_A15_0: GEL Output: DX4GSR0[25]: QSGERR on Rank1 has ** No Error **
arm_A15_0: GEL Output: DX4GSR0[24]: QSGERR on Rank0 has ** Error **
arm_A15_0: GEL Output: DX4GSR0[6]: WLERR has ** No Error **
arm_A15_0: GEL Output: Byte Lane 5:
arm_A15_0: GEL Output: DX5GSR2[6]: WEERR has ** No Error **
arm_A15_0: GEL Output: DX5GSR2[4]: REERR has ** No Error **
arm_A15_0: GEL Output: DX5GSR2[2]: WDERR has ** No Error **
arm_A15_0: GEL Output: DX5GSR2[0]: RDERR has ** Error **
arm_A15_0: GEL Output: DX5GSR0[25]: QSGERR on Rank1 has ** No Error **
arm_A15_0: GEL Output: DX5GSR0[24]: QSGERR on Rank0 has ** Error **
arm_A15_0: GEL Output: DX5GSR0[6]: WLERR has ** No Error **
arm_A15_0: GEL Output: Byte Lane 6:
arm_A15_0: GEL Output: DX6GSR2[6]: WEERR has ** No Error **
arm_A15_0: GEL Output: DX6GSR2[4]: REERR has ** No Error **
arm_A15_0: GEL Output: DX6GSR2[2]: WDERR has ** No Error **
arm_A15_0: GEL Output: DX6GSR2[0]: RDERR has ** Error **
arm_A15_0: GEL Output: DX6GSR0[25]: QSGERR on Rank1 has ** No Error **
arm_A15_0: GEL Output: DX6GSR0[24]: QSGERR on Rank0 has ** Error **
arm_A15_0: GEL Output: DX6GSR0[6]: WLERR has ** No Error **
arm_A15_0: GEL Output: Byte Lane 7:
arm_A15_0: GEL Output: DX7GSR2[6]: WEERR has ** No Error **
arm_A15_0: GEL Output: DX7GSR2[4]: REERR has ** No Error **
arm_A15_0: GEL Output: DX7GSR2[2]: WDERR has ** No Error **
arm_A15_0: GEL Output: DX7GSR2[0]: RDERR has ** Error **
arm_A15_0: GEL Output: DX7GSR0[25]: QSGERR on Rank1 has ** No Error **
arm_A15_0: GEL Output: DX7GSR0[24]: QSGERR on Rank0 has ** Error **
arm_A15_0: GEL Output: DX7GSR0[6]: WLERR has ** No Error **
arm_A15_0: GEL Output: Byte Lane 8:
arm_A15_0: GEL Output: DX8GSR2[6]: WEERR has ** No Error **
arm_A15_0: GEL Output: DX8GSR2[4]: REERR has ** No Error **
arm_A15_0: GEL Output: DX8GSR2[2]: WDERR has ** No Error **
arm_A15_0: GEL Output: DX8GSR2[0]: RDERR has ** No Error **
arm_A15_0: GEL Output: DX8GSR0[25]: QSGERR on Rank1 has ** No Error **
arm_A15_0: GEL Output: DX8GSR0[24]: QSGERR on Rank0 has ** No Error **
arm_A15_0: GEL Output: DX8GSR0[6]: WLERR has ** No Error **
arm_A15_0: GEL Output: ****************************************************************************************************************
