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Development board to support 4x 50 Mbit/s video stream

Simon Ogg
Prodigy 10 points
Other Parts Discussed in Thread: TMS320DM6437

Hello,

I am wondering if anyone could help me, I'm trying to setup up or obtain a demonstrater to stream video (composite or BT656) to and from an FPGA. Ideally I want to do this using off the shelf with ready made boards.

Composite/BT656 <==216 MBit/s ==> DSP <== 4x 50 Mbit/s==> FPGA <== 66 Msymbols/s ==> PHY

Currently I have been given a setup consisting of a TMS320DM6437 EVM from spectrum digital cabled to an ADS-V4-LX-DEV from avnet., but I rapidly find this just will not cut it as the key problem is that the TMS320DM6437EVM has only 2 McASP serial channels wired to the connector at the max frequency these will run at is 40 MHz (so at best I could acheieve 2x 40 Mbit/s channels). I then looked at the possiblity of using the EMIF, but this is 8 bits and asynchronous and some quick hand calculation i came up with about 80 Mbit/s to and from dsp (based on approx 4 clk per wr, 5 clk per rd, 1 turn around and fpga clk of 100 MHz .... effectively 1 Byte read and 1 Byte write @ 10 MHz) so cant use this either.

The main problem is establishing the 4x50 Mbit/s second channel between the DSP and FPGA and I am thinking the best option is to perhaps look at the some of the other DSPs in the family which use a synchronous 32 bit or 64 bit wide EMIF and then map the channels to addres spaces in the FPGA.

I am wondering if anyone could suggest or know of a suitable board that has:

1. Composited video (or BT656) in and out

2. Audio in out

3. DSP

4. FPGA connected to 32/64 bit synchronous DSP EMIF (or other simple port which can support a bw of 4x50 Mbit/s uplink and downlink between FPGA and DSP)

 

Many thanks, Simon

 

  • 0
    TI__Mastermind 41665 points

    The more modern Davinci devices no longer contain the wide synchronous EMIFs that used to come on most of our DSPs, it has been replaced largely by the smaller asynchronous EMIF that is meant primarily for flash and the DDR2 interface which is designed only to interface with DDR2 modules. This being said, to get what you describe you would have to look back to older generations of devices, namely the DM642, which actually has a XC2S300E FPGA on its EVM that has a 32bit EMIF interface, however note that the higher bandwidth video data is actually piped through a video port connection on the FPGA.

    Based on what you are trying to do you may want to consider implementing a video port in the FPGA and taking the data in that way, as the video port is essentially a uni directional synchronous parallel bus, if you could use the VPBE to connect to the FPGA  you would have more than enough bandwidth, though this does assume the data only flows in one direction.