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no of simultaneous transfer possible in edma3 in dm6446

manoj6581
Prodigy 240 points

Hi all,

i have a small question wat are the no of simultaneous dma transfers possible in edma3 is it 2 since there are only 2 TCs . then what do the word channel indicate.could i not do more no of simultaneous transfers since there are as many as 64 channels. does the word channel indicate the presence of any physical channels or does it indicate only the no of events that can be triggered.

  • 0
    TI__Mastermind 37340 points

    DMA channels share the TCs; therefore, theoretically only two transfers can be happening at any one time.  See Figure 2-1 in EDMA UG (http://focus.ti.com/lit/ug/sprue23d/sprue23d.pdf)

  • 0
    TI__Mastermind 41665 points

    Just a bit of an elaboration on Juan's post, keep in mind that most end points within the device can only be accessed by one accessor at any given time, for example if you have two DMA transfers that access DDR2 as the source or destination, than they cannot be truly happening simultaneously as they are sharing the same DDR2 bus resource, on the other hand if you have one DMA servicing a serial port and copying data into internal memory while another DMA is transferring data from the EMIFA to the DDR2 space than they can be happening simultaneously (up to 2 max limited by # of TCs as Juan says).

  • 0 in reply to Bernie Thompson TI
    Prodigy 240 points

    hi bernie and Gonzales

    thanks for the clarification , can u please tell me how to configure the parallel transfers (how to use the edma efficietly by configuring the TC s ) so that i can achieve max throughput .is there any documentation available on scheduling transfers between the 2 TCs. i require to transfer Y,U,V components so i thought of using 3 channels since any way only 2 can be done at time how to configure them so that they can be transfered in least time . i am using dman3 framework and i can see the transfers are going in serial i am expecting only 1 TC is being used for the transfer how can i use both the TCs so that my transfer will be fast

    thanks

    manoj

  • 0 in reply to manoj6581
    TI__Mastermind 41665 points

    If you are accessing YUV data than I would guess that this data is in external memory? In the case of external memory you can only have one transfer going on as the DDR can only be used by one accessor at a given point in time, so even if you had it configured so that you used multiple TCs you would not be able to transfer simultaneously, so there may not be much point in attempting to adjust the TC being used.

    You can adjust which TC that the transfer ultimately goes to by assigning a transfer to queue0 or queue1 with the DMAQNUMn registers as discussed in section 4.3.1.4 of SPRUE23, queue0 goest to TC0 and queue1 goes to TC1 as discussed in section 2.10.4 of SPRUE23. Note that the queue0 is higher priority than queue1 and the way the priority is setup queue1 can be data starved so by changing this you may see other system level issues, see section 2.1.1 of the silicon errata for details.