RTOS/AM5728: Inconsistent SPI transfers

Hi Eric,

   I am Using phytech phycore-AM5728 board for this testing.

  I have tried MCSPI example in loop, I have attached the Image from the oscilloscope.I am doing a single transaction multiple times with a delay of 10 ms, I probed the sclk line, I can see some transaction missing. 

I above Image The time between two cursor is 10 ms, Which is proper but In below Image the time between two cursor is 38 ms i.e some transactions are missing in between.

I can clearly see some transactions are missing between the two cursors.

The clock speed 1 MHz is programmed as below. The spiInClk is 40 MHz spiOutClk is 1 MHz. The below code is found in path 

/ti/pdk_am57xx_1_0_8/packages/ti/csl/src/ip/mcspi/V0/priv/mcspi.c

void McSPIClkConfig(uint32_t baseAddr,
                    uint32_t spiInClk,
                    uint32_t spiOutClk,
                    uint32_t chNum,
                    uint32_t clkMode)
{
    uint32_t fRatio;
    uint32_t spiClk;
    uint32_t clkD;
    /*TI_INSPECTED 105 D: MISRAC_2012_R.2.2
     * "Reason - LDRA tool issue not able to understand HW_WR_FIELD32 macros
     *" */
    uint32_t extClk;

    /* Calculate the value of fRatio. */
    fRatio = spiInClk / spiOutClk;

    /* If fRatio is not a power of 2, set granularity of 1 clock cycle */
    if ((uint32_t) 0U != (fRatio & (fRatio - 1U)))
    {
        /* Set the clock granularity to 1 clock cycle.*/
        HW_WR_FIELD32(
            baseAddr + MCSPI_CHCONF(chNum),
            MCSPI_CH0CONF_CLKG,
            MCSPI_CH0CONF_CLKG_ONECYCLE);

        /* Calculate the ratios clkD and extClk based on fClk */
        extClk = (fRatio - 1U) >> 4U;
        clkD   = (fRatio - 1U) & (uint32_t) MCSPI_CLKD_MASK;

        /* Set the extClk field of MCSPI_CHCTRL register.*/
        HW_WR_FIELD32(
            baseAddr + MCSPI_CHCTRL(chNum),
            MCSPI_CH0CTRL_EXTCLK,
            extClk);
    }
    else
    {
        clkD   = 0U;
        /* Clock granularity of power of 2.*/
        HW_WR_FIELD32(
            baseAddr + MCSPI_CHCONF(chNum),
            MCSPI_CH0CONF_CLKG,
            MCSPI_CH0CONF_CLKG_POWERTWO);

        while (1U != fRatio)
        {
            fRatio /= 2U;
            clkD++;
        }
    }

    /* Configure the clkD field of MCSPI_CHCONF register.*/
    HW_WR_FIELD32(
        baseAddr + MCSPI_CHCONF(chNum),
        MCSPI_CH0CONF_CLKD,
        clkD);

    /*Clearing the clkMode field of MCSPI_CHCONF register.*/
    spiClk = HW_RD_REG32(baseAddr + MCSPI_CHCONF(chNum));

    spiClk &= ~((uint32_t) MCSPI_CH0CONF_PHA_MASK | (uint32_t) MCSPI_CH3CONF_POL_MASK);

    /* Configure the clkMode of MCSPI_CHCONF register.*/
    spiClk |= (clkMode & (MCSPI_CH0CONF_PHA_MASK | MCSPI_CH3CONF_POL_MASK));

    HW_WR_REG32(baseAddr + MCSPI_CHCONF(chNum), spiClk);
}

Hi Eric,

     The expected capture from the oscilloscope is continuous spikes with a 10 ms delay in between, But some spikes are missing as seen from the pictures. There are no groups of spikes  in above pictures,The second picture signifies that there is transaction miss in between, when I measure the delay between 2 spikes in between in the second picture it is 38 ms( as shown by cursor ) which should be 10 ms which clearly signifies there are 2 transaction miss in between. I have attached the snippet of the code.

 while(1) {

    transaction.count = McSPI_DATA_COUNT;
    transaction.txBuf = gTxBuffer;
    transaction.rxBuf = gRxBuffer;
    ret = SPI_transfer(gSpiHandle, &transaction);
    Task_sleep(10); // 10 ms delay
}

Currently I am trying with a blocking mode of transfer, The captured above pictures are for blocking mode. When I changed it to callback mode I am seeing more transaction miss than blocking mode.