C5515 GPIO input timing

Bernhard,

It looks like that you want to use GPIOs as a parallel interface to the ADC. The numbers you were referred above is for generating interrupt via a GPIO port, not for read data via GPIO ports. Read data from GPIO ports will take more cycles.

1) What is the max sampling rate you want to acheive?

2) Will all GPIOs be inputs? How are you going to detect that data is ready?

Regards,

Peter Chung

On Figure 6-42, it shows how input pulse relates to which edge triggering (rise / fall) used in interrupt  enable registers IOINTEDY1 / IOINTEDY2. You can also refer to

http://www.ti.com/litv/pdf/sprufo4

Peter,

Thank you for your answer. The background of my question is that we want to migrate from the C5409 to a C55x. With the C5409 we had the ADC connected to the external memory interface and we where able to achieve a sampling rate equal to the DSP clock rate of 40MHz. We would like to achieve the same sampling rate with the C55x. A higher DSP clock rate is acceptable.

From fig. 6-17 in the data sheet it seems that a read cylcle with asynchronus memory connected to the EMIF is at least 3 cycles long. Therefore I considered using the GPIO instead. From your answer I conclude that the GPIO read timing is not specified. The data sheet does not seem to show anything regarding this. Do you still see any chance to program a continious read operation faster than 3 cycles? We don't need a ready signal. The ADC receives a clock derived from the DSP clock out. There is no other hardware connected to the external data bus.

If that is not possible, can the EMIF be used to at least achieve a 3 cycle long continious read operation?

We consider not only the C5515 but also the C5510. The only advantage of the C5515 over the 5510 seems to be the FFT accelarator.

regards,

Bernhard

Bernhard,

With C5515, how are you going to provide clock to the ADC? Are you going to use another GPIO pin?

I will check the cycle count of back-to-back GPIO reading with C5515 and get back to you.

Best Regards,

Peter Chung

Peter,

I considered using another GPIO pin for creating the clock signal for the ADC. However, this will certainly be to slow. We can derive the clock from the clock out signal of the DSP by deviding it down to the sampling rate achievable with the DSP.

Thanks for your efforts.

regards,

Bernhard

Bernhard,

I have tried to read GPIO register back-to-back with "repeat". With 50 iterations, I got 75 cycles, which means it took 1.5 CPU cycle/ read including repeat.

 repeat (#(50-1)

 AC0 = *port(#0x1C08) 

Regarding the latency, according to design, the latency of updating the GPIO register is 2 cycles, which means the minimum latency from a GPIO port to CPU will be 3.5cycles. 

Conclusion: the max GPIO reading speed is ~CPU clock/1.5. I think you can get 40MHz GPIO reading speed with C5515/05. However, if you need to do something else simultaneoulsy, it will be less than that.

Peter,

The latency of 3.5 cycles is not a problem.

I can reproduce your result. Howerver, what does it mean that one operation takes an average of 1.5 cycles? I would assume that the operation takes either one or two cycles. If the average is 1.5 cycle it means that every second opration needs 2 cycles, right? 

We observe that the CPU needs 1.5 cycles per read operation. How can we know that this is also the minimum time the GPIO pin needs to be active?

Is there any further documentation about this GPIO timing?

regards,

Bernhard

Bernhard,

I am OOO today, so I can't use CCS with a target boad. If you could, please read GPIO multiple time as below without repeat (20 ~ 30 times).

AC0 = *port(#0x1C08) 

AC0 = *port(#0x1C08) 

AC0 = *port(#0x1C08) 

.....

It will give you clear idea about CPU cycle in reading GPIO register back-to-back. 

BTW, I am not sure if I understood "...the minimum time the GPIO pin needs to be active?". Could you explain more detail? 

Regards,

Peter Chung

Peter,

I did'nt put my qestion very clearly. What I need to know is when in the CPU cycle the processor takes over the data from the GPIO pin. There is no cycle diagram for the GPIO in the data sheet like the one in fig. 6-17 for the EMIF.

I'm still wondering how it is possible for the CPU to do fractional cycles.

regards,

Bernhard

Bernhard,

I have a hard time to understand the reason of your request. The path CPU reads GPIO register is quite complicated and you may not need it at all. I think important thing for you to know is effective CPU cycle counts when CPU reads GPIO register back-to-back.

Regards,

Peter Chung

Peter,

what I'm looking for is a diagram like Figure 5-18 in SPRS076L. Is this available for the 5515?

regards,

Bernhard

Sorry, I can't find SPRS076L from www.ti.com. Would you please give me a link or name of the document?

SPRSO76 is the 5510 datasheet. The SPRSO7L I was referring to is a previous version. Fig. 5-18 is present in both.

Bernhard,

Thank you. I now understand what you are looking for. Yes, I know why you are looking for that information. I will check out if we have the information you need for the C5515. 

Best Regards,

Peter Chung

Peter,

Too bad, but thanks for the information.

regards,

Bernhard