dm6443 watchdog can not reset chip

I am not aware of any bug with WD timer and driver has been around for quite some time; we will need to investigate this further.  If you can provide source code (ideally a small test case) to help us reproduce what you are seeing, this would be ideal.

Thanks for your reply

the source code in   arch/arm/mach-davinci/time.c

/***********************begin************************/

void davinci_watchdog_reset(void) {
    volatile davinci_timer_regs_t *davinci_wdt =
        (volatile davinci_timer_regs_t *)IO_ADDRESS(DAVINCI_WDOG_BASE);

    davinci_wdt->tcr = 0x0;        /* disable timer */
    davinci_wdt->tgcr = 0x0;    /* reset timer */
        davinci_wdt->tgcr = 0x8;    /* configure timer2 as 64-bit */
        davinci_wdt->tgcr |= 0x3;    /* release timer from reset */
    davinci_wdt->tim12 = 0;        /* clear counter and period regs */
    davinci_wdt->tim34 = 0;
    davinci_wdt->prd12 =  0;
    davinci_wdt->prd34 =  0;
    davinci_wdt->wdtcr |= 0x4000;    /* enable watchdog timer */

    /* put watchdog in pre-active state */
    davinci_wdt->wdtcr = 0xA5C64000;

    /* put watchdog in active state */
    davinci_wdt->wdtcr = 0xDA7E4000;   

    /* write an invalid value to the WDKEY field to trigger
     * a watchdog reset */
    davinci_wdt->wdtcr = 0x00004000;
}

/***********************end************************/

This function does not work normally.

I had asked my friend who had achieved dm6446's watchdog.

He told me that DM6446 has same problem which is resolved by change UBL's source code(clear 0x01C41a20)

What he did is uncoment these code.

;/* Do this for enabling a WDT initiated reset this is a workaround
       ;   for a chip bug.  Not required under normal situations */
;        LDR R6, P1394
;        MOV R10, #0x0        
;        STR R10, [R6]

I had tried to clear this register when linux  boot up(not in ubl), it does not work.

0x01c41a20  is a reserved register in DM6446/6443 datasheet.

So i had no ideal how follow it.

Must the register be clear in bootloader?

Does this register had any relationshit to other module??I must clear it before the related module initiation?

Is there any different between 6446 and 6443?

What DVSDK (and thus u-boot version) version are you using?  I was aware if this work-around and have given it to customers in the past (it was discovered mid-2006); however, I thought this was fixed in the latest software release.  I will investigate further to see if it is indeed fixed or not.

FYI, this work-around code

LDR R6, P1394

MOV R10, #0x0

STR R10, [R6]

P1394 address - 0x01c41a20

needs to happen in UBL before L1/L2 memory initialization and after GEM reset completion; without this work-around WDT will hang on reset as you are currently experiencing.  Also, I am aware this register address (0x01c41a20) is marked as reserved and will see if I can get you more details on it.  Thank you for your patience...

I see.

In fact we don't use u-boot neither DVSDK.

I will refer to u-boot source code, and try to modify our bootloader and clear this register in right position.

Thanks.

Hi,

I am having the same problem.  Did clearing this register work for you?

Thanks,

Mike