Hi,
My customer are using C6678 and they are having problem at DDR3 write access.
I attached file which the problem are written. Please take a look.
The problem doesn't always occur.
Occasionally occurs when the "board power on" -> write access -> "board power off"
process is repeated.
They are using evm6678_ddr.c which are included in Processor SDK,
and set the value of register calculated from the DDR3 calculation spread sheet which TI provided.
At the moment, we suspect the leveling failure.
At initialization of DDR3, we set initial value to each WRLVL_INIT_RATIO and GTLVL_INIT_RATIO.
My customer are using partial leveling and want to know the WRLVL and GTLVL ratio result value
issued by leveling to comapre with the above initial value.
Are there any registers which we can check the result value of WRLVL and GTLVL ratio?
Also, please let me know if there is anything to check against this problem.
best regards,
g.f.
