TMS320C6678: DDR3 write access issue

Hi Yordan,

I got DDR3 initialization code and Excel Calculation spreadsheet from our customer
and checked if there are any wrong setting.
It seems there are no problem in initialization code and spreadsheets,
but may be I missed looking something so if you don't mind could you check the attach files?

By the way, they are using Winbond DDR3(W634GU6MB11I).
www.winbond.com/.../w634gu6mb_a01.pdf
This DDR3's speed grade are 1833MHz but they refer to parameter of
1333MHz memory in datasheet and they set those value to the Excel spreadsheet.

best regard,
g.f.

DDR3 PHY Calc v11 for E2E.xlsx

DDR3 Register Calc v4 for E2E.xlsx

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#include <ti/csl/csl_bootcfgAux.h>
#include <ti/csl/cslr_device.h>
#include <ti/csl/csl_xmcAux.h>
#include <ti/csl/csl_emif4fAux.h>
#include <ti/csl/hw_types.h>

#include "board_internal.h"

extern void BOARD_delay(uint32_t usecs);

static void xmc_add_emif_cfg_region()
{
    /* mapping for ddr emif registers XMPAX*2 */
    CSL_XMC_XMPAXL    mpaxl;
    CSL_XMC_XMPAXH    mpaxh;

    /* base addr + seg size (64KB)*/    //"1B"-->"B" by xj */
    mpaxh.bAddr     = (0x2100000B >> 12);
    mpaxh.segSize   = (0x2100000B & 0x0000001F);

    /* replacement addr + perm*/
    mpaxl.rAddr     = 0x100000;
    mpaxl.sr        = 1;
    mpaxl.sw        = 1;
    mpaxl.sx        = 1;
    mpaxl.ur        = 1;
    mpaxl.uw        = 1;
    mpaxl.ux        = 1;

    /* set the xmpax for index2 */
    CSL_XMC_setXMPAXH(2, &mpaxh);
    CSL_XMC_setXMPAXL(2, &mpaxl);
}

/* Set the desired DDR3 configuration -- assumes 66.67 MHz DDR3 clock input */
Board_STATUS Board_DDR3Init()
{
    Board_STATUS             status = BOARD_SOK;
    uint32_t                 ddr3config, ddrPhyCtrl;
    uint8_t                  ddrPHYReadLatency;
    EMIF4F_TIMING1_CONFIG    sdram_tim1;
    EMIF4F_TIMING2_CONFIG    sdram_tim2;
    EMIF4F_TIMING3_CONFIG    sdram_tim3;
    EMIF4F_OUTPUT_IMP_CONFIG zqcfg;
    EMIF4F_PWR_MGMT_CONFIG   pwrmgmtcfg;
    EMIF4F_SDRAM_CONFIG      sdramcfg;

	xmc_add_emif_cfg_region();

    CSL_BootCfgUnlockKicker();

    /**************** 3.3 Leveling Register Configuration ********************/
    CSL_BootCfgGetDDRConfig(0, &ddr3config);
    ddr3config &= ~(0x007FE000);  // clear ctrl_slave_ratio field
    CSL_BootCfgSetDDRConfig(0, ddr3config);

    CSL_BootCfgGetDDRConfig(0, &ddr3config);
    ddr3config |= 0x00200000;     // set ctrl_slave_ratio to 0x100
    CSL_BootCfgSetDDRConfig(0, ddr3config);

    CSL_BootCfgGetDDRConfig(12, &ddr3config);
    ddr3config |= 0x08000000;    // Set invert_clkout = 1
    CSL_BootCfgSetDDRConfig(12, ddr3config);

    CSL_BootCfgGetDDRConfig(0, &ddr3config);
    ddr3config |= 0xF;            // set dll_lock_diff to 15
    CSL_BootCfgSetDDRConfig(0, ddr3config);

    CSL_BootCfgGetDDRConfig(23, &ddr3config);
    ddr3config |= 0x00000200;    // See section 4.2.1, set for partial automatic levelling
    CSL_BootCfgSetDDRConfig(23, ddr3config);

    /**************** 3.3 Partial Automatic Leveling ********************/
    ddr3config = 0x000000D2;
    CSL_BootCfgSetDDRConfig(2, ddr3config);
    ddr3config = 0x000000CA;
    CSL_BootCfgSetDDRConfig(3, ddr3config);
    ddr3config = 0x000000C9;
    CSL_BootCfgSetDDRConfig(4, ddr3config);
    ddr3config = 0x000000C3;
    CSL_BootCfgSetDDRConfig(5, ddr3config);
    ddr3config = 0x000000AD;
    CSL_BootCfgSetDDRConfig(6, ddr3config);
    ddr3config = 0x000000AF;
    CSL_BootCfgSetDDRConfig(7, ddr3config);
    ddr3config = 0x00000086;
    CSL_BootCfgSetDDRConfig(8, ddr3config);
    ddr3config = 0x0000007C;
    CSL_BootCfgSetDDRConfig(9, ddr3config);
    ddr3config = 0x00000000;
    CSL_BootCfgSetDDRConfig(10, ddr3config);

    ddr3config = 0x00000158;
    CSL_BootCfgSetDDRConfig(14, ddr3config);
    ddr3config = 0x00000160;
    CSL_BootCfgSetDDRConfig(15, ddr3config);
    ddr3config = 0x0000012E;
    CSL_BootCfgSetDDRConfig(16, ddr3config);
    ddr3config = 0x00000134;
    CSL_BootCfgSetDDRConfig(17, ddr3config);
    ddr3config = 0x00000117;
    CSL_BootCfgSetDDRConfig(18, ddr3config);
    ddr3config = 0x00000115;
    CSL_BootCfgSetDDRConfig(19, ddr3config);
    ddr3config = 0x0000010B;
    CSL_BootCfgSetDDRConfig(20, ddr3config);
    ddr3config = 0x00000115;
    CSL_BootCfgSetDDRConfig(21, ddr3config);
    ddr3config = 0x00000000;
    CSL_BootCfgSetDDRConfig(22, ddr3config);

    /*Do a PHY reset. Toggle DDR_PHY_CTRL_1 bit 15 0->1->0 */
    CSL_EMIF4F_GetPhyControl(&ddrPhyCtrl, &ddrPHYReadLatency);
    ddrPhyCtrl &= ~(0x00008000);
    CSL_EMIF4F_SetPhyControl(ddrPhyCtrl, ddrPHYReadLatency);

    CSL_EMIF4F_GetPhyControl(&ddrPhyCtrl, &ddrPHYReadLatency);
    ddrPhyCtrl |= (0x00008000);
    CSL_EMIF4F_SetPhyControl(ddrPhyCtrl, ddrPHYReadLatency);

    CSL_EMIF4F_GetPhyControl(&ddrPhyCtrl, &ddrPHYReadLatency);
    ddrPhyCtrl &= ~(0x00008000);
    CSL_EMIF4F_SetPhyControl(ddrPhyCtrl, ddrPHYReadLatency);

    /***************** 3.4 Basic Controller and DRAM configuration ************/
    /* enable configuration */
    /*    hEmif->SDRAM_REF_CTRL    = 0x00005161; */
    CSL_EMIF4F_EnableInitRefresh();
    CSL_EMIF4F_SetRefreshRate(0x5161);

    /*    hEmif->SDRAM_TIM_1   = 0x1113783C; */
    sdram_tim1.t_wtr    = 0x4;
    sdram_tim1.t_rrd    = 0x7;
    sdram_tim1.t_rc     = 0x20;
    sdram_tim1.t_ras    = 0x17;
    sdram_tim1.t_wr     = 0x9;
    sdram_tim1.t_rcd    = 0x8;
    sdram_tim1.t_rp     = 0x8;
    CSL_EMIF4F_SetTiming1Config(&sdram_tim1);

    /*    hEmif->SDRAM_TIM_2   = 0x30B37FE3; */
    sdram_tim2.t_cke    = 0x3;
    sdram_tim2.t_rtp    = 0x4;
    sdram_tim2.t_xsrd   = 0x1FF;
    sdram_tim2.t_xsnr   = 0x0B3;
    sdram_tim2.t_xp     = 0x3;
    sdram_tim2.t_odt    = 0x0;
    CSL_EMIF4F_SetTiming2Config(&sdram_tim2);

    /*    hEmif->SDRAM_TIM_3   = 0x559F8ADF; */
    sdram_tim3.t_rasMax     = 0xF;
    sdram_tim3.t_rfc        = 0x0AD;
    sdram_tim3.t_tdqsckmax  = 0;
    sdram_tim3.zq_zqcs      = 0x3F;
    sdram_tim3.t_ckesr      = 4;
    sdram_tim3.t_csta       = 0x5;
    sdram_tim3.t_pdll_ul    = 0x5;
    CSL_EMIF4F_SetTiming3Config(&sdram_tim3);

    /*    hEmif->DDR_PHY_CTRL_1   = 0x0010010C; */
    ddrPHYReadLatency       = 0x0C;
    ddrPhyCtrl              = (0x08008);
    CSL_EMIF4F_SetPhyControl(ddrPhyCtrl, ddrPHYReadLatency);

    /*    hEmif->ZQ_CONFIG        = 0x70073214; */
    /*    (Calc Value)hEmif->ZQ_CONFIG        = 0x70074019;*/
    zqcfg.zqRefInterval     = 0x3214;
    zqcfg.zqZQCLMult        = 3;
    zqcfg.zqZQCLInterval    = 1;
    zqcfg.zqSFEXITEn        = 1;
    zqcfg.zqDualCSEn        = 1;
    zqcfg.zqCS0En           = 1;
    zqcfg.zqCS1En           = 0;
    CSL_EMIF4F_SetOutputImpedanceConfig(&zqcfg);

    /*    hEmif->PWR_MGMT_CTRL    = 0x0; */
    pwrmgmtcfg.csTime       = 0;
    pwrmgmtcfg.srTime       = 0;
    pwrmgmtcfg.lpMode       = 0;
    pwrmgmtcfg.dpdEnable    = 0;
    pwrmgmtcfg.pdTime       = 0;
    CSL_EMIF4F_SetPowerMgmtConfig(&pwrmgmtcfg);

    /* New value with DYN_ODT disabled and SDRAM_DRIVE = RZQ/7 */
    /*    hEmif->SDRAM_CONFIG     = 0x63063332; */
    CSL_EMIF4F_GetSDRAMConfig(&sdramcfg);
    sdramcfg.pageSize       = 2;
    sdramcfg.eBank          = 0;
    sdramcfg.iBank          = 3;
    sdramcfg.rowSize        = 6;
    sdramcfg.CASLatency     = 0xC; //-> This should be 0xA for Winbond DDR3(1333Mhz)
    sdramcfg.narrowMode     = 0;
    sdramcfg.CASWriteLat    = 2;
    sdramcfg.SDRAMDrive     = 1;
    sdramcfg.disableDLL     = 0;
    sdramcfg.dynODT         = 0;
    sdramcfg.ddrDDQS        = 0;
    sdramcfg.ddrTerm        = 3;
    sdramcfg.iBankPos       = 0;
    sdramcfg.type           = 3;
    CSL_EMIF4F_SetSDRAMConfig(&sdramcfg);

    BOARD_delay(600); /*Wait 600us for HW init to complete*/

    /* Refresh rate = (7.8*666MHz] */
    /*    hEmif->SDRAM_REF_CTRL   = 0x00001458;     */
    CSL_EMIF4F_SetRefreshRate(0x00001458);

    /***************** 4.2.1 Partial automatic leveling ************/
    /*    hEmif->RDWR_LVL_RMP_CTRL      =  0x80000000; */
    CSL_EMIF4F_SetLevelingRampControlInfo(1, 0, 0, 0, 0);

    /* Trigger full leveling - This ignores read DQS leveling result and uses ratio forced value */
    /*    hEmif->RDWR_LVL_CTRL          =  0x80000000; */
    CSL_EMIF4F_SetLevelingControlInfo(1, 0, 0, 0, 0);

    /************************************************************
      Wait for min 1048576 DDR clock cycles for leveling to complete
      = 1048576 * 1.5ns = 1572864ns = 1.57ms.
      Actual time = ~10-15 ms
     **************************************************************/
    BOARD_delay(30000); //Wait 3ms for leveling to complete

    return status;
}

g.f.,

There are 2 options in the wiki text.  It shows a length report generated by a CAD tool that then was dropped into a spreadsheet so that the calculations could be added.  This is shown in "EVM DDR3 Rules.pdf".  The spreadsheet "KeyStone DDR3 Length Rules Template.xlsx" is a draft tool that can be used where you must manually add the lengths into the existing template.  Either solution is adequate.

Tom

g.f.,

Please let us know when it is available.

Tom

g.f.,

Do you have an estimate on the availability of the length matching report for this board?

Tom

g.f.,

Thanks for the update.  We will update it when provided.

Tom

g.f.,

Is this going to happen in the next week?  If not, I recommend that we close this thread.  Then later you can create a new one that is linked to this one.

Tom

Hi Tom,

I'm so sorry for keep you waiting so long time.
I got the report from my customer, so please take a look at the report.

And I have additional information from my customer.
The issue will occur at one of Byte Lane 4, 5, or 6.
And the issue won't occur simutaneously in those byte lane.
When issue occur, the phases of DQS and CLK are 180 degrees out of phase compared to normal operation.
Please take a look at waveform diagram and question#1 in page.1 of attached file.

And they also have a question about Write latency register value.
Please take a look at page.2 of attached file.

best regards,
g.f.

KeyStone DDR3 Length Rules Template v1p0.xlsx

C6678_DDR3 write issue.pdf

g.f.,

I have reviewed the length report tables and agree that the numbers are pretty good.  There are some discrepancies but they should not result in the leveling failures that you observe.  I also compared the lengths from the new tables back with the lengths in the PHY_CALC worksheet submitted last month.  The numbers are close but do not quite match.  I recommend that you update the lengths in the PHY_CALC worksheet and check whether the failure results change.

You report that the leveling process fails sometimes and that it passes sometimes.  Do all boards fail intermittently or only certain boards?  How many boards have you built?  How many fail?  For those that fail, what is the ratio of failures to total number of tests - i.e. if turned on 10 times, they normally fail 2 or 3 times.

Have you tried running the DDR interface at a slower speed?  You can simply reduce the PLL frequency while keeping all other settings unchanged.  Does this resolve the problem?

You indicated in the checklist that there were 4 vias per data group route.  Why so many?  Is the board using an HDI (microvia) stackup and you are counting the microvias and through vias separately?

Tom

g.f.,

I was looking at the C-code.  This appears to be the standard RTOS code provided by TI.  It contains a call to a function called BOARD_delay.  How is this implemented?  This delay is required.  You must implement the BOARD_delay function such that your optimizing compiler does not delete it.  Please test and make sure that the BOARD_delay function is working as expected.  Broken delay functions can result in intermittent leveling failures that are resolved by repeated leveling trials.

Tom

Hi Tom,

I will share the answer from my customer.

>I recommend that you update the lengths in the PHY_CALC worksheet
>and check whether the failure results change.

The lenght in the PHY_CALC worksheet is more accurate value.
The difference is the length of the damping resistor of the DQS/DQ line.
But even they didn't take into account this phenomenon occurred.

>Do all boards fail intermittently or only certain boards?  How many boards have you built?
>How many fail?  For those that fail, what is the ratio of failures to total number of tests - i.e. if turned on 10 times,
>they normally fail 2 or 3 times.

They made 7 boards and the issue will occur in 6 boards.

After the DSP boot up, the DDR3 memory test is automatically executed.
In their system configuration, if the memory test have passed
the system will going to power-OFF the DSP and then power-on the DSP then repeat the test,
or if the memory test have failed the system will stop the operation.
During this memory test, there is board which operation will stop after 7 times of power-off/on the DSP and this is the shortest.

Please take a look at the attached file about the issue.
(This file is same file which I posted a month ago)

>You indicated in the checklist that there were 4 vias per data group route. 
>Why so many?  Is the board using an HDI (microvia) stackup and you are counting the microvias and through vias separately?

Since the damping resistor(10ohm) are inserted in the DQS/DQ line, the number of VIA have increased.

The customer are checking the Board_delay() and going to test with lower PLL frequency right now.

best regards,
g.f.

4401.C6678 DDR3 Write issue.pdf

g.f.,

Multiple topics here:

1.  Regarding difference in the trace routing and the PHY_CALC worksheet:

The expectation is that the routed lengths in the length matching table are the same lengths loaded into the PHY_CALC worksheet.  In both cases, the lengths need to be proportional to signal delay.  If you believe the length of the resistor body is additive to the delay, then it should appear in both spreadsheets.  Similarly, we normally ignore via barrel length but if the variations are significant, that can be added too.

2.  Regarding board failure rate:

You built 7 prototypes and 6 of them fail occasionally.  The worst board fails after 7 trials.  Therefore, more stable boards take more iterations to fail.  Please provide an estimate of the average number of loops before failure for all 6 boards that intermittently fail?

3.  Regarding damping resistors on DQ and DQS lines:

Series damping resistors are not recommended on the DQ and DQS lines with the C6678 DSP.  The DDR PHY on this DSP as well as the DDR3 SDRAMs contain output buffers that are impedance compensated.  This impedance compensation controls the output impedance across variations in temperature, supply voltage and silicon process.  Addition of these damping resistors result in additional vias.  Additional vias degrade signal integrity and this is not allowed.

4.  Regarding document attached describing leveling failure:

I agree that this shows a leveling failure.  You have not provided enough information to determine whether this is a write leveling failure or a read leveling failure.  When you have a board in the failed state, read the block of memory multiple times.  If the values change on subsequent reads, then you are seeing read leveling failures.  If you always read the same contents showing the data shift, then you are getting write leveling failures.

Tom

Hi Tom,

I got answer from my customer.

When they made PLL frequnecy slower the issue didn't occured.
The following are what they tried:
*************************************************************
Case1:
When DDR registers values was setup for DDR3-1333 memory,
they setup PLL frequency to lower frequency 533MHz.

The values of PLL register is as follow:
Input CLK = 100MHz
PLLD=3, PLLM=16, OUTPUTDIV=1

They tried with 2 boards and running the memory test 2000 loops,
the test have been passed and no issue occured so far.

Case2:
When DDR registers values was setup for DDR3-1600 memory,
they setup PLL frequency to lower frequency 666MHz.
(I will attach the CALC spreed sheet for DDR3-1600 memory)

DDR3 PHY Calc v11 for 1600.xlsx

DDR3 Register Calc v4 for winbond_1600.xlsx

The values of PLL register is as follow:
Input CLK = 100MHz
PLLD=3, PLLM=20, OUTPUTDIV=1

They tried with 2 boards and running the memory test 1000 loops,
the test have been passed and no issue occured so far.
*************************************************************

As a result of trial with lowering the frequency of DDR PLL,
the issue no longer occurs.
From this result, what kind of cause can be considered?

And, are there any problem to setup PLL frequency to lower frequency 666MHz
even DDR3 register value are setup for DDR3-1600 memory?

best regards,
g.f.

g.f.,

The DDR3 interface on the C6678 is only rated for 1333MT/s (666MHz clock).  You must not operate it at 1600MT/s (800MHz clock).  You can use SDRAMs that have a speed rating for 1600 or 1866 but you must use the settings from the datasheet that correspond with 1333.  Therefore the 2 spreadsheets provided that configure the DDR3 interface to operation with an 800MHz clock are not valid.

In case 1, you used register DDR configuration values for 1333MT/s but then configured the PLL to generate a 533MHz clock for 1066MT/s operation.  This was successful and resulted in robust leveling configuration on 2 boards for 2000 iterations.  This is a good data point in that it shows the board is fundamentally implemented correctly.  Operating at this reduced speed provides additional timing margin to the accesses.

I am not clear on case 2.  You claim to have used the register settings for 1600MT/s.  As stated above, these settings are not valid.  Then you ran the interface at 1333Mt/s (666MHz clock from the PLL) and report success again on 2 boards.  This does not make sense.  What happens with these 2 boards if you simply restore the 1333MT/s register settings and keep the PLL set for 666MHz?  In theory, this should still be robust.

Tom

g.f.,

>>3. Regarding damping resistors on DQ and DQS lines:
>I told the customer that damping resistors on DQ and DQS lines aren't recommended and remove it from the lines,
>but now they are asking if dumping resistance can be a direct cause of this issue.

I already explained this in my 9/27 post.  It is not the damping resistors that are a problem (assuming they are on the order of 10 ohms).  The problem is the additional 2 vias on each DQ and DQS route.  Each via creates an impedance discontinuity.  Degradation for each via accumulates and erodes signal integrity and timing margin.  Our routing guidelines only allow a maximum of 2 vias per route.

I am still waiting for confirmation that the board_delay function is properly working (from my 9/25 post).  Simple delay loops can be stripped by the compiler.  The delay must be implemented so that it provides the delay time specified.  Multiple times I have seen leveling failures like yours caused by improper delay loop implementations.

Tom

g.f.,

I just realized that the PLL settings do not look correct.  Please have these double checked.  The equation from the DM is:

CLK = CLKIN × ((PLLM+1) ÷ ((OUTPUT_DIVIDE+1) × (PLLD+1)))

Therefore:

Input CLK = 100MHz, PLLD=3, PLLM=16, OUTPUTDIV=1 yields 262.5MHz

Input CLK = 100MHz, PLLD=3, PLLM=20, OUTPUTDIV=1 yields 262.5MHz

To get the proper speeds, you need:

Input CLK = 100MHz, PLLD=2, PLLM=39, OUTPUTDIV=1 yields 666.667MHz

Input CLK = 100MHz, PLLD=2, PLLM=31, OUTPUTDIV=1 yields 533.333MHz

Please verify the DDRCLOCK using an oscilloscope.  You might then need to replicate the tests previously reported.

Tom

g.f.,

Please go back to Case 1 and Case 2 from last week.  Rerun these tests while verifying the DDR clock using a scope probe.  Also, please re-check the configuration used for each.  Once you provide the results from these tests, we can determine how to proceed.

Tom

Hi Tom,

The customer tried the memory test again.
They sent me the attached files of DDR_CLK signal probed by oscilloscope and the DDR3 register values of each test cases.

Customer DDR_CLK signal.xlsx

Customer DDR3 Register Values.xlsx

Test Case1:
Configured DDR3 register values are  for DDR3-1333, DDR_CLK=533MHz
Resutl: Test passed

Test Case2:
Configured DDR3 register values are for DDR3-1600, DDR_CLK=666MHz
Result: Test passed

Test Case3:
Configured DDR3 register values are for DDR3-1333, DDR_CLK=666MHz
(They used same board of Test Case2)
Result: Test failed

The DDR3 memory which they are using is Winbond [W634GU6MB11I(DDR3L-1866)].

w634gu6mb_a01.pdf

best regards,
g.f.

g.f.,

These results are consistent with the previous data.  That is good.  The summaries of the register settings are also good to have.  Can they also provide the PHY_CALC and REG_CALC spreadsheets used to calculated these register settings.

Tom

g.f.,

You will need to find the speed bin table in the datasheet for the slowest part that will be placed in the board.  If this is a -107 device, then you will need to pull values form the DDR3L-1866 Speed Bins table.  In this table there will be a column for the -107 speed grade device.  The lower portion of this table contains CL and CWL settings based on clock speed.  Operating the DDR at 1333MT/s requires a clock running at 666MHz which has a period of 1.5ns.  Therefore, you will need to find the row(s) that have period boundaries 1.5ns min and 1.875ns max.  CL=10 with CWL=7 is a common combination for this clock rate.

Tom

g.f.,

Correct, as shown on page 135 of the DM provided.  Note that there are other timing parameters needed that will be pulled form the 1866 columns in the AC Characteristics table starting on page 138.

Tom

Hi Tom,

I'm sorry for the delay.
I got the test result and appropriate spreadsheet from my customer
Please take a look at the attached spreadsheet.

There are two types of spreadsheets for 1333MT/s and 1600MT/s.
The value of each parameter in spreadsheet for 1333MT/s was pulled from 1866 colums.
But the value in spreadsheet for 1666MT/s was pulled from  1600 colums.
Because from DDR3 datasheet, it seems there are no CAS Latency value
which can be chosen for 1600(1.25ns) in 1866 colums.

DDR3 PHY Calc v11 for 1333.xlsx

DDR3 Register Calc v4 for 1333.xlsx

8054.DDR3 PHY Calc v11 for 1600.xlsx

DDR3 Register Calc v4 for 1600.xlsx

The tests were done by using same board.
The test details which they did and the result is as follow:

Test sequence(it is same memory test as one I posted before):
***************************************************************
After the DSP boot up, the DDR3 memory test is automatically executed.
In their system configuration, if the memory test have passed
the system will going to power-OFF the DSP and then power-on the DSP then repeat the test,
or if the memory test have failed the system will stop the operation.
***************************************************************

The result:
*1333MT/s@666MHz DDR_CLK
 It seems the test failing once per twice.
 DSP boot up -> Test passed -> power-off -> power-on -> DSP boot up -> Test fails

*1333MT/s@533MHz DDR_CLK
 No fail. It passed the test 2500 times so far without failing.

*1600MT/s@666MHz DDR_CLK
 No fail. It passed the test 1000 times so far without failing.
 (They set the CL=10, CWL=7)

best regards,
g.f.

g.f.,

Customer should contact Winbond about the missing CL/CWL settings for 1600MT/s (1.25ns) in the speed bin table for the 1866 speed grade device.  This appears to be a gap in their datasheet for this speed part.

Tom

g.f.,

You refer to configurations as 1333MT/s and 1600MT/s.  I believe that the files provided are a matched set (PHY_CALC and REG_CALC) for each speed configuration.  Is this correct?  What result do you see if you use the REG_CALC from 1333MT/s and the PHY_CALC from 1600 with a clock speed of 666MHz?

Tom

Hi Tom,

I'm sorry about taking so long time to reply to you.

>Customer should contact Winbond about the missing CL/CWL settings for 1600MT/s (1.25ns)
>in the speed bin table for the 1866 speed grade device. 
>This appears to be a gap in their datasheet for this speed part.

They are contacting to Winbond right now.
As soon as they get CL/CWL vaules from Winbond, they will going to test.

> I believe that the files provided are a matched set (PHY_CALC and REG_CALC) for each speed configuration. 
> Is this correct?

Yes, it is correct. The files which we provided are matched set for each speed configuration.

>What result do you see if you use the REG_CALC from 1333MT/s and
>the PHY_CALC from 1600 with a clock speed of 666MHz?

The memory test passed about 7600 times without failure.

best regards,
g.f.

Hi Tom,

Thank you for the reply.

I'm very sorry but I have additional question about the effect of temperature.

>The PHY CALC worksheet computes initial values that are used for the adaptive leveling logic in the PHY. 
>This does not need exact values.  It only needs to be an approximate starting point.

I understood that initial values only need to be an approximate starting point.
But if the temperature of environment changed, doesn't configured starting point may be shifted out of valid range?
If there are possibility of the configured starting point shifted out of valid range by temperature,
should they find the middle point in the valid range by increasing the stripline delay(Cell C2) for example
and then set that calculated value to the registers as starting point?

For example, starting from 172.7[ps/inch] in Cell C2 which are invalid when DDR CLK is set to 666.667[MHz]
then increase the Cell C2 and find the maximum, minimum of valid C2 value.
And then select the middle value between maximum and minimum of valid C2 value.

best regards,
g.f.