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DPLL spread spectrum clocking

Gavin Jones59637
Prodigy 10 points
Other Parts Discussed in Thread: AM3517

Hello,

I am trying to enable spread spectrum clocking on an AM3517. The target clock is the LCD pixel clock, derived from DPLL4 (peripheral DPLL) output DSS1_ALWON_FCLK.

Following these steps:

  1. Write 0x0000 0005 to CONTROL_PER_DPLL_SPREADING (at 0x48002458). This should set SPREADING_RATE to "01", SPREADING_AMPLITUDE to "01" (x6).
  2. Write 0x0000 0015 to CONTROL_PER_DPLL_SPREADING (at 0x48002458). To set the enable bit.

I expect bit CONTROL_PER_DPLL_SPREADING.PER_SPREADING_ENABLE_STATUS to go high, but it does not.

My questions are:

  • What is the function of bit PER_SPREADING_ENABLE_STATUS? Should I expect it to go high?
  • If it should, what steps am I missing?

DPLL4 is running using M = 432, N = 12. Status shows as "locked" as expected. Setting DPLL4 into low power stop mode whilst making this change doesn't seem to help.

Thanks.

  • 0
    Guru 10570 points

    Hello,

    I encountered the same problem too.
    I would like to clarify about below questions.

    1. When I set XXX_SPREADING_ENABLE_STATUS, does XXX_SPREADING_ENABLE_STATUS is set to 1?

    2. Should I ensure that the XXX_SPREADING_ENABLE_STATUS bit is 1, after I set Spread Spectrum Clocking Configuration?

    Could you please any advice?

    Best regards, RY

  • 0 in reply to RY9983
    Guru 10570 points

    I would like to reduce the electric reflection.
    I need about whether the SPREAD SPECTRUM can use as this function.

    Trivial     information is OK.
    Does anyone give some hints, please?

    Best regards, RY