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TCI6630K2L: Need reference design for TCI6630K2L DSP

Part Number: TCI6630K2L
Other Parts Discussed in Thread: 66AK2L06, RFSDK, TIDEP0081

Hello,

I am searching for TCI6630K2L's reference design. In the device page, Ti do not provide reference design. Please suggest that where I can get reference design..

Regards,

Muthu

  • Hello,
    The reference would be the einfoChips TCI6630K2L / 66AK2L06 EVM. " www.ti.com/.../xtcievmk2lx "

    There are third party provides Comm Agility Ltd, and Azcom Ltd as well.

    Regards,
    Joe Quintal
  • Hi Joe Quintal,

    Thank you for your reply. I got einfo reference design but I could not find reference design of Comm Agility Ltd for TCI6630K2L. Please provide the link if you have...

    Thanks,

    Muthu

  • Hello,

    Comm Agility Ltd, and Azcom Ltd provide design services and prebuilt designs, I don't think they have a reference design to copy.   Being a third party engineering group, you have to contract them for their IP.

    The example design is based on the eInfochips TCI6630K2L / 66AK2L06 EVM, and the TI designs for the JESD data converters there.  TIDEP0081 discusses the RFSDK software, data converters, and 66ak2l06.   

    The einfoChips EVM schematic has to be reviewed to convert the test connections and port utilization for your specific design. " www.ti.com/.../xtcievmk2lx "

    The AMCC, FMC1, and FMC2 connectors from the EVM are studied to determine what port- functionality is needed.  Also note for the EVM that the FPGA provides further multiplexing and GPIO extension, your design may not need these features.

    Regards,

    Joe Quintal

     

  • Hi Joe Quintal,

    Previously, we have selected TCI6630K2L because of Our transceiver AD9371 have JESD204B interface which is compatible to the DSP. As AD9371 is not meeting our requirements, we are going for AD9361 which do not have JESD204B interface instead it is having 24-bit(pin) parallel bus.So, can u suggest a DSP that have similar spec like TCI6630K2L but has to be able to connect directly with AD9361 ?

    Thanks,
    Muthu
  • Hello,
    There is no Keystone processor with LVDS differential IO interface and DFE. If you have 12 data, Frame, and Clock for each ADC and DAC, (unidirectional) this is 14x4 differential LVDS signals. You would need to transcode this to another interface to use the Keystone I or Keystone II processors.

    SRIO(4) Unidrectional - 5Gbps
    PCIe (2) Bidirectional - 5Gbps
    EMIF 16bit data transfer - 100e6 Transfer rate
    CPRI (2) Bidirectional - TBD Gbps, with carrier aggregation
    so you need a CPLD/FPGA to convert one of these packet data standard to an timed data <-> timed FIFO <-> LVDS
    You need to include some synchronization point.

    Regards,
    Joe Quintal
  • Hi Joe Quintal,

    Thanks...Ok, we are going to keep FPGA in our design so that one side of the FPGA will talk to DSP over JESD204B and another side will talk to RF transceiver using LVDS. Right now, our problem is to find FPGA with JESD204B core IP. FPGA vendors are charging separately for this. So, please share if you know any FPGA which supports up to 4 JESD204B lanes at low cost to connect with TCI6630K2L...

    Thanks,

    Muthu

  • Hello,
    I have not studied this for several years. On a previous project we compared to large tier1 FPGA provides with JESD204B core. They were comparable in price and features. There are several FPGA companies that have hard-IP conversion of one standard to another. This is the only suggestion for low cost, be careful of low features or low support as a result.
    Regards,
    Joe Quintal