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AM3352: C15 cache array data format question

Ilya Kogan77
Intellectual 355 points
Part Number: AM3352

I am looking for additional explanation on Data 0/Data 1 registers
(ARM DDI 0344K, 3.2.74 c15, L1 system array debug data registers).
D0 contains 32-bit data array information (Table 3-153)
D1 contains 6-bit data array information (Table 3-154)

So there are 38 bits of data. So far I was not able to find any additional information on the meaning of the bits.

Would be great to get similar information on all other registers mentioned in 3.2.74 (TLB CAM, TLB ATTR, TLB PA, HVAB, tag, data, GHB, and BTB data operations)

  • 0
    Intellectual 355 points
    In the meantime I tried examples in section
    3.2.78 c15, L1 data array operations

    It looks like all C15 instructions cause undefined instruction exceptions.
    Sadly a recommendation to use these instructions came form TI when my question about testing instruction/data cache was answered.
    Does it mean that these instructions are not actually implemented?
  • 0 in reply to Ilya Kogan77
    TI__Guru* 86550 points
    Ilya, it appears from the ARM documentation that those registers are only accessible in secure privileged mode. On the AM335x, the only CP15 registers that are accessible in secure mode are described in section "3.1.4.2.2. Secure Monitor Calls to Access CP15 Registers". Unfortunately, it does not include the ones you are looking for.

    Regards,
    James