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insight into dma and ddr2 interaction for dm643x

MattLipsey
Genius 3575 points

I have an image in ddr2 captured by the video port  where each row is much longer than each column.  If I perform image processing by row, there is good potential for cache thrashing since I can only fit a few long rows in L1D cache.  However if I switch to processing by column, I can fit many more columns in cache and could make much more efficient reuse of memory.  I don't believe that I can use the video port to swap the x & y dimensions as the image is being captured... although by all means correct me if I'm wrong.  I do know that I can use the edma to swap the array dimension as I move the data from ddr2 to L2 sram, which I can then cache into L1D for processing.

I am blissfully ignorant of the details of ddr2 operation, although I'm pretty sure that sequential address transfers are more efficient.  Can anyone shed some light on the 'optimum' access pattern to ddr2?  For example, if I transfer 1 byte from each row at a time what kind of overhead am I going to pay?  Is there a magic number of sequential byte accesses for maximum bandwidth?  Any answers or places to look for answers would be appreciated.  I can't seem to find a definite answer in the data sheets I have been perusing.

  • Genius 3575 points

    I think I have found the answer to my question.  SDRAM is read by first activating a row, then reading data from that row, then deactivating that row before repeating the process.  It is also possible to read a burst of data with one command (4 or 8 words for my particular device).  So it pays to at least read a multiple of this burst value from each row.  After that, it's just a tradeoff between the penalty paid for accessing different rows and the latency that it takes the dma to get all the columns for that number of rows.  Sorry to answer my own post, maybe this will save someone else some time.