• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 3 answers
  • Subscribers 98 subscribers
  • Views 632 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM5718: IOSET questions

Denny%20Yang99373
Expert 3805 points
Part Number: AM5718
Other Parts Discussed in Thread: AM5726

Hi all,

We have checked am5718 idk board pr1_mii1_rxd2 have mapped to pad F9. And have some questions:

1, How to set IOSET1/2/3? when do IOSET if it will set a group of IOs or only one IO pin.

2, AM5726 datasheet if different with am5718 about PRU_MII ioset. Does this mean am5726 F9 can't been set to pr1_mii1_rxd2?

3, How to use Virtual and Manual I/O Timing Modes? what does this function used for? 

thanks!

 

BR,

Denny

  • 0
    TI__Guru**** 161600 points
    Hi Denny,

    1) The IOSETs (a_delay & g_delay) are different for each pin. If you see 7.5 Virtual and Manual I/O Timing Modes, Table 7-2. Modes Summary, you will see that the corresponding virtual/manual IOSETs Virtual or Manual IO Mode Name column is a link to a table that specifies the IO delays for each pin.

    2). The fact that datasheet recommendations for IOSETS in AM5726 and AM5718 are different DOESN'T mean that you can't set F9 as PR1_MII1_RXD2, it means that you should consider specifying different a_delay and g_delay depending on which SoC are you using.

    3). This is explained in details in Section 18.4.6.1.5 Virtual IO Timing Modes and Section 18.4.6.1.6 Manual IO Timing Modes of the device TRM.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    TI__Expert 3805 points

    Hi Yordan,

    Thanks for your feedback. But I haven't understand how to set the register about IOSET.

    Could you please make a example help me to quick understand?

    which registers should been set if we want PR1_MII1_RXD2 use pad F9?

    thanks!

    BR,
    Denny

  • 0 in reply to Denny%20Yang99373
    TI__Guru**** 161600 points
    Ok, ball F9 can be configured as: vout1_d5, emu7, vin4a_d21, vin3a_d21, obs3, obs19, pr2_edc_latch0_in, pr2_pru0_gpi2, pr2_pru0_gpo2 or gpio8_5. I am not sure where in the datasheet do you see that F9 can be configured as PR1_MII1_RXD2.

    PR1_MII1_RXD2 can be pinmuxed on D6. And there is NO requirement to set IO delays (manual or virtual IOSET) for PR1_MII2_RXD2 listed in the datasheet.
    When D6 is configured as vin2a_d17 or vin2b_d6 you should set the timing values listed in Table 7-7. Manual Functions Mapping for VIP1. The register is listed in the table: CFG_VIN2A_D17_IN. The calculations for a_delay & g_delay MUST be done using the PINMUX tool, you should NOT try to calculate by hand.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    TI__Expert 3805 points

    Yordan,

    You can check am5718 idk schematic.

    just search "PR1_MII1_RXD2". it connect to "AM57XX_VOUT1_D5/F9" via U103.

    BR,
    Denny

  • 0 in reply to Denny%20Yang99373
    TI__Guru**** 161600 points
    Hi Denny,

    I see, there is additional mux inside the PRUICSS, that is why the datasheet states that when in muxmode 12 F9 is pr2_pru0_gpi2. When remuxing within the PRUICSS you can configure it to be PR1_MII1_RXD2...

    So in this case you should refer to Table 7-161. Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET1 Direct Input mode. You can see that A_DELAY=0 & G_DELAY=0, therefore you DON'T have to set any IODELAYS in CFG_VOUT1_D5_IN. You can confirm this by checking const struct iodelay_cfg_entry iodelay_cfg_array_am571x_idk[] in u-boot/board/ti/am57xx/mux_data.h ==> There is NO configuration for CFG_VOUT1_D5_IN. So no need to set any IOSET for PR1_MII1_RXD2.

    Best Regards,
    Yordan