Hello,
With starterware we are using both MPU A15 cores and want to configure the MPU_MMU to use cache but still retain the ability to use inter-core variables with DSP and IPU cores. We also want to have both A15 cores with MMU enabled running concurently. It seems like this would be possible by programming the MMU with specific tables/descriptors. To start we used the starterware example tables for MMU as a reference (found in mmu_a15_data_validation_app):
/* Set level one descriptor attributes */
gAttrs.descriptorType = MMU_A15_DESCRIPTOR_TYPE_BLOCK;
gAttrs.attrIndx = MMU_A15_ATTR_INDEX_2;
gAttrs.nonSecure = MMU_A15_NON_SECURE_ENABLE;
gAttrs.accPerm = MMU_A15_ACC_PERM_RW_ANY_PL; /*Read Write at any PL*/
/* Set level one descriptor */
virtualAddr = 0x0, phyAddr = 0x0;
MMUA15SetFirstLevelDesc(&gMmuTable, virtualAddr, phyAddr, &gAttrs);
virtualAddr = 0x40000000, phyAddr = 0x40000000;
MMUA15SetFirstLevelDesc(&gMmuTable, virtualAddr, phyAddr, &gAttrs);
virtualAddr = 0x80000000, phyAddr = 0x80000000;
MMUA15SetFirstLevelDesc(&gMmuTable, virtualAddr, phyAddr, &gAttrs);
virtualAddr = 0xc0000000, phyAddr = 0x80000000;
MMUA15SetFirstLevelDesc(&gMmuTable, virtualAddr, phyAddr, &gAttrs);
With the values above if you attempt to print while MMU is enabled nothing gets printed. Similarly any attempt to use mailbox functions while MMU is enabled will fail. We can get both those to work by changing the 0x40000000 entry to MMU_A15_ATTR_INDEX_1.
1. Is it correct in that chaging to MMU_A15_ATR_INDEX_1 it is just disabling cache for this address block?
2. Would this be the recommended way for retaining access to UART, Mailbox, DMA,...?
When MMU is enabled we've observed inter-core variables that exist in external DDR mismatch between cores. An example is writing to a variable in DDR space on an A15 with MMU enabled and having an IPU core check the value. When MMU is enabled the IPU core does not read back what A15 just wrote but if MMU is disabled then IPU core reads back the correct value every time.
3. Is the mismatch due to A15 using cache and not actually writing it back to DDR?
4. Is there a way to make sure what A15 writes while MMU is enabled gets written to DDR?
5. What is the correct way to create a 16MiB section in DDR that would have its own table entry and use MMU_A15_ATR_INDEX_1? Couldn't find how to change sizes in the function MMUA15SetFirstLevelDesc().
Thank you,
JMG
