McASP clock speed

Gregory Duperon

Expert 7430 points

I have a customer attempting to pair a Sitara processor with an audio codec over I2S.

What are McASP interface capabilities in terms of MCLK, WCLK, BCLK?

I'm assuming McASP is 512kHz and 1.024MHz capable, correct?

over 7 years ago

0 Biser Gatchev-XID over 7 years ago

TI__Guru**** 393215 points

Gregory,

Can you please post which Sitara device you are asking about?

0 Gregory Duperon over 7 years ago in reply to Biser Gatchev-XID

TI__Expert 7430 points

Biser,

A specific version of Sitara hasn't actually been selected just yet. Customer is wondering two things:

(1) Can the Sitara processors currently available support thos bus speeds over McASP?
(2) If so, which Sitara processors are capable of this?

Thanks.

Greg

0 Biser Gatchev-XID over 7 years ago in reply to Gregory Duperon

TI__Guru**** 393215 points

McASP timings are listed in the relevant section of the device datasheet. Minimum ACLKR/X and AHCLKR/X cycle time is 20ns (50MHz maximum clock frequency).

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McASP clock speed