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RTOS/AM5746: Cache coherency

Kaka
Guru 24520 points

Part Number: AM5746
Other Parts Discussed in Thread: AM5726

Tool/software: TI-RTOS

Hi TI Experts,

Please let me confirm the following question.


[Question.1-1]
  Can AM5746 set the write-back for cache?
[Question.1-2]
  Can AM5726 support the data sharing on SDRAM or on-chip RAM between Cortex-A15 and Cortex-M4?
[Question1-3]
  Can AM5746 stay in the cache coherency with above situation??

[Question.2]
  If AM5746 support the above case, can the cortex-M read the correct data on cache in following case?

1. Write the data to sharing memory region by Cortex-A15
2. This value is on cache (Not reflect on actually memory yet)
3. Access the same memory region by Cortex-M4
-> At this time, can Cortex-M4 read the write back data on cache?

If you have any qeustions, please let me know.
Best regards.
Kaka

  • 0
    TI__Guru**** 393215 points
    The RTOS team have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Guru* 95265 points
    Hi,

    1-1 Yes, AM57x supports cache write-back.
    1-2 Yes, we supports data share between ARM and M4 through shared memory, this memory can be DDR or OCMC. And the memory region can be configured as cached or non-cached. This framework is called as IPC: software-dl.ti.com/.../Foundational_Components_IPC.html
    1-3 No, there is no cache coherency between A15 and M4. The application needs to maintain this. Good news is that, if you use TI IPC framework, you only need to do some high level configuration on CPU side and share region side. The rest is handled for you by the framework.

    For Q2, same as 1-3.

    Regards, Eric
  • 0
    Guru 24520 points

    Part Number: AM5746

    Tool/software: TI-RTOS

    Hi TI Experts,

    Please let me confirm the following question.

    [Question.1]
    Can AM5746 stay in the cache coherency with following situation??
    1. AM5746 set the write-back for cache
    2. MPU cores share the data sharing on SDRAM or on-chip RAM between BUS Master IPs like PCIe or EDMA.

    [Question.2]
    Can AM5746 stay in the cache coherency with following situation??
    1. AM5746 set the write-back for cache
    2. IPU cores share the data sharing on SDRAM or on-chip RAM between BUS Master IPs like PCIe or EDMA.

    If you have any question, please let me know.

    Best regards.

    Kaka

  • 0 in reply to Kaka
    TI__Guru* 95265 points
    Hi,

    [Question.1]
    Can AM5746 stay in the cache coherency with following situation??
    1. AM5746 set the write-back for cache
    2. MPU cores share the data sharing on SDRAM or on-chip RAM between BUS Master IPs like PCIe or EDMA.
    [No, on A15 the application needs to keep the coherency through cache invalidate or invalidate and writeback. In the PCIE driver for AM572x A15, there are functions cache_invalidate() and cache_writeback() in drv\pcie\example\sample\src\pcie_sample.c]

    [Question.2]
    Can AM5746 stay in the cache coherency with following situation??
    1. AM5746 set the write-back for cache
    2. IPU cores share the data sharing on SDRAM or on-chip RAM between BUS Master IPs like PCIe or EDMA.
    [No, on M4 the application needs to keep the coherency through cache invalidate or invalidate and writeback]

    Regards, Eric